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smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=AwRn2o9P; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2793E606A330; Sun, 15 Nov 2026 00:18:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=AwRn2o9P Received: by smtp.kernel.org (Postfix) with ESMTPSA id 329351F000C6; Sun, 15 Nov 2026 00:18:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794701936; bh=EZxe3fLIr15GcaixYMlvps3d1PnaVZ20JcGF+Wr3YZ8=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=AwRn2o9PJPdY4Tsh8f7dj4K/jfCtYiXAKcWLF0yQ0QLmDqxcF9BGCWNZxE6Bj2NIn XdwEkc/MHOgMrlCheM4punrxGrDokcTG1uhVaU+DiH2gVgVvbhS53D3X7cF47QVBbp cRZ4N7IOemShmlDKlVb8zfUDmzoHSPgVLg48sPmNtyI20H4lCtejLmjm8B970Cx2RE 0dbQCcf+hj4gB4YkN5uFUq3mAPJGv+NqA57memdEMrOGlOCsAr82vqQEushYZf51c2 TaLFps8Tt0tFlvCYDKgoZeyOSGvZ7/SF1ZbkEQjhV0bycOVX1oHJbYrg6VsKkx9eSC 8VMn+oxSdhmNw== Date: Sun, 15 Nov 2026 00:18:49 +0000 From: Jonathan Cameron To: Archit Anant Cc: dlechner@baylibre.com, andy@kernel.org, nuno.sa@analog.com, u.kleine-koenig@baylibre.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, joshua.crofts1@gmail.com, Andy Shevchenko Subject: Re: [PATCH v6 11/11] iio: adc: ti-ads1015: Replace custom shift macros with FIELD_PREP/GET Message-ID: <20261115001849.17c18851@jic23-hlaptop> In-Reply-To: <20261109165805.31160-6-architanant5@gmail.com> References: <20261109165805.31160-1-architanant5@gmail.com> <20261109165805.31160-6-architanant5@gmail.com> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-pc-linux-gnu) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 9 Nov 2026 22:28:05 +0530 Archit Anant wrote: > The driver currently uses custom _SHIFT macros and manual bitwise > operations to read and write to the configuration register. > > Modernize the bitwise logic by replacing all manual shifts with the > standard FIELD_PREP() and FIELD_GET() macros from . > This improves readability and prevents potential bitwise errors. > > Remove the now-unused _SHIFT macros from the top of the file. > > Suggested-by: Jonathan Cameron > Suggested-by: Andy Shevchenko > Signed-off-by: Archit Anant > --- > drivers/iio/adc/ti-ads1015.c | 79 ++++++++++++++++++++---------------- > 1 file changed, 44 insertions(+), 35 deletions(-) > > diff --git a/drivers/iio/adc/ti-ads1015.c b/drivers/iio/adc/ti-ads1015.c > index 2c3ba1b91aac4..8f7ec61314363 100644 > --- a/drivers/iio/adc/ti-ads1015.c > +++ b/drivers/iio/adc/ti-ads1015.c > @@ -11,6 +11,7 @@ > * * 0x4B - ADDR connected to SCL > */ > > +#include > #include > #include > #include > @@ -38,15 +39,6 @@ > #define ADS1015_LO_THRESH_REG 0x02 > #define ADS1015_HI_THRESH_REG 0x03 > > -#define ADS1015_CFG_COMP_QUE_SHIFT 0 > -#define ADS1015_CFG_COMP_LAT_SHIFT 2 > -#define ADS1015_CFG_COMP_POL_SHIFT 3 > -#define ADS1015_CFG_COMP_MODE_SHIFT 4 > -#define ADS1015_CFG_DR_SHIFT 5 > -#define ADS1015_CFG_MOD_SHIFT 8 > -#define ADS1015_CFG_PGA_SHIFT 9 > -#define ADS1015_CFG_MUX_SHIFT 12 > - > #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0) > #define ADS1015_CFG_COMP_LAT_MASK BIT(2) > #define ADS1015_CFG_COMP_POL_MASK BIT(3) > @@ -382,17 +374,24 @@ int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) > > pga = data->channel_data[chan].pga; > dr = data->channel_data[chan].data_rate; > - mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK | > - ADS1015_CFG_DR_MASK; > - cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT | > - dr << ADS1015_CFG_DR_SHIFT; > I'm probably being inconsistent across versions, but at least looking at it this time, I prefer the building up common cfg and mask first, then adding the extra bits in the following. > if (ads1015_event_channel_enabled(data)) { > - mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK; > - cfg |= data->thresh_data[chan].comp_queue << > - ADS1015_CFG_COMP_QUE_SHIFT | > - data->comp_mode << > - ADS1015_CFG_COMP_MODE_SHIFT; > + mask = ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK | > + ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK | > + ADS1015_CFG_DR_MASK; > + cfg = FIELD_PREP(ADS1015_CFG_MUX_MASK, chan) | > + FIELD_PREP(ADS1015_CFG_PGA_MASK, pga) | > + FIELD_PREP(ADS1015_CFG_DR_MASK, dr) | > + FIELD_PREP(ADS1015_CFG_COMP_QUE_MASK, > + data->thresh_data[chan].comp_queue) | > + FIELD_PREP(ADS1015_CFG_COMP_MODE_MASK, > + data->comp_mode); > + } else { > + mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK | > + ADS1015_CFG_DR_MASK; > + cfg = FIELD_PREP(ADS1015_CFG_MUX_MASK, chan) | > + FIELD_PREP(ADS1015_CFG_PGA_MASK, pga) | > + FIELD_PREP(ADS1015_CFG_DR_MASK, dr); > }