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Wed, 3 Mar 2021 09:57:18 +0000 Subject: Re: [PATCH 2/2] iommu: arm-smmu-v3: Report domain nesting info reuqired for stage1 To: Auger Eric , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, virtualization@lists.linux-foundation.org Cc: joro@8bytes.org, will.deacon@arm.com, mst@redhat.com, robin.murphy@arm.com, jean-philippe@linaro.org, alex.williamson@redhat.com, kevin.tian@intel.com, jacob.jun.pan@linux.intel.com, yi.l.liu@intel.com, Lorenzo.Pieralisi@arm.com, shameerali.kolothum.thodi@huawei.com References: <20210212105859.8445-1-vivek.gautam@arm.com> <20210212105859.8445-3-vivek.gautam@arm.com> <0708b0b2-78f7-e55c-21a7-3c49eb5141df@redhat.com> From: Vivek Kumar Gautam Message-ID: <2050ee9b-527c-f8c6-445a-4786d144496a@arm.com> Date: Wed, 3 Mar 2021 15:27:09 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 In-Reply-To: <0708b0b2-78f7-e55c-21a7-3c49eb5141df@redhat.com> Content-Type: text/plain; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2021 09:57:26.7693 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fba4f5d-5813-48c4-c19b-08d8de2ac04a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT003.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR08MB2754 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Eric, On 2/12/21 11:43 PM, Auger Eric wrote: > Hi Vivek, > > On 2/12/21 11:58 AM, Vivek Gautam wrote: >> Update nested domain information required for stage1 page table. > > s/reuqired/required in the commit title My bad! Will correct it. >> >> Signed-off-by: Vivek Gautam >> --- >> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++-- >> 1 file changed, 14 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> index c11dd3940583..728018921fae 100644 >> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >> @@ -2555,6 +2555,7 @@ static int arm_smmu_domain_nesting_info(struct arm_smmu_domain *smmu_domain, >> void *data) >> { >> struct iommu_nesting_info *info = (struct iommu_nesting_info *)data; >> + struct arm_smmu_device *smmu = smmu_domain->smmu; >> unsigned int size; >> >> if (!info || smmu_domain->stage != ARM_SMMU_DOMAIN_NESTED) >> @@ -2571,9 +2572,20 @@ static int arm_smmu_domain_nesting_info(struct arm_smmu_domain *smmu_domain, >> return 0; >> } >> >> - /* report an empty iommu_nesting_info for now */ >> - memset(info, 0x0, size); >> + /* Update the nesting info as required for stage1 page tables */ >> + info->addr_width = smmu->ias; >> + info->format = IOMMU_PASID_FORMAT_ARM_SMMU_V3; >> + info->features = IOMMU_NESTING_FEAT_BIND_PGTBL | > I understood IOMMU_NESTING_FEAT_BIND_PGTBL advertises the requirement to > bind tables per PASID, ie. passing iommu_gpasid_bind_data. > In ARM case I guess you plan to use attach/detach_pasid_table API with > iommu_pasid_table_config struct. So I understood we should add a new > feature here. Right, the idea is to let vfio know that we support pasid table binding, and I thought we could use the same flag. But clearly that's not the case. I will add a new feature. >> + IOMMU_NESTING_FEAT_PAGE_RESP | >> + IOMMU_NESTING_FEAT_CACHE_INVLD; >> + info->pasid_bits = smmu->ssid_bits; >> + info->vendor.smmuv3.asid_bits = smmu->asid_bits; >> + info->vendor.smmuv3.pgtbl_fmt = ARM_64_LPAE_S1; >> + memset(&info->padding, 0x0, 12); >> + memset(&info->vendor.smmuv3.padding, 0x0, 9); >> + >> info->argsz = size; >> + > spurious new line Sure, will correct this. >> return 0; >> } >> >> > Thanks Vivek