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([2a02:3035:6e0:9052:36d8:1776:f263:97eb]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390daf7dbcsm15922705e9.30.2025.02.05.02.01.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Feb 2025 02:02:00 -0800 (PST) Message-ID: <206a6ada-1ef9-47f3-b1cf-fb1a1540e95c@canonical.com> Date: Wed, 5 Feb 2025 11:01:58 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/5] riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader To: Hal Feng Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, E Shattow , Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou References: <20250203013730.269558-1-e@freeshell.de> <20250203013730.269558-6-e@freeshell.de> <25B3D8909DBCC21B+43663a76-4afa-44ae-95e2-3a8792de614c@linux.starfivetech.com> Content-Language: en-US From: Heinrich Schuchardt In-Reply-To: <25B3D8909DBCC21B+43663a76-4afa-44ae-95e2-3a8792de614c@linux.starfivetech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2/5/25 08:57, Hal Feng wrote: > On 2/3/2025 9:37 AM, E Shattow wrote: >> Add bootph-pre-ram hinting to jh7110-common.dtsi: >> - i2c5_pins and i2c-pins subnode for connection to eeprom >> - eeprom node >> - qspi flash configuration subnode >> - memory node >> - uart0 for serial console >> >> With this the U-Boot SPL secondary program loader may drop such >> overrides when using dt-rebasing with JH7110 OF_UPSTREAM board targets. >> >> Signed-off-by: E Shattow >> --- >> arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi >> index 30c5f3487c8b..c9e7ae59ee7c 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi >> @@ -28,6 +28,7 @@ chosen { >> memory@40000000 { >> device_type = "memory"; >> reg = <0x0 0x40000000 0x1 0x0>; >> + bootph-pre-ram; >> }; >> >> gpio-restart { >> @@ -247,6 +248,7 @@ emmc_vdd: aldo4 { >> }; >> >> eeprom@50 { >> + bootph-pre-ram; >> compatible = "atmel,24c04"; >> reg = <0x50>; >> pagesize = <16>; >> @@ -323,6 +325,7 @@ &qspi { >> nor_flash: flash@0 { >> compatible = "jedec,spi-nor"; >> reg = <0>; >> + bootph-pre-ram; >> cdns,read-delay = <2>; >> spi-max-frequency = <100000000>; >> cdns,tshsl-ns = <1>; >> @@ -405,6 +408,7 @@ GPOEN_SYS_I2C2_DATA, >> }; >> >> i2c5_pins: i2c5-0 { >> + bootph-pre-ram; >> i2c-pins { >> pinmux = > GPOEN_SYS_I2C5_CLK, >> @@ -413,6 +417,7 @@ GPI_SYS_I2C5_CLK)>, >> GPOEN_SYS_I2C5_DATA, >> GPI_SYS_I2C5_DATA)>; >> bias-disable; /* external pull-up */ >> + bootph-pre-ram; >> input-enable; >> input-schmitt-enable; >> }; >> @@ -641,6 +646,7 @@ GPOEN_DISABLE, >> }; >> >> &uart0 { >> + bootph-pre-ram; >> clock-frequency = <24000000>; >> pinctrl-names = "default"; >> pinctrl-0 = <&uart0_pins>; > > What about &mmc0, &mmc1, &qspi, &sysgpio, &mmc0_pins, &mmc1_pins, &i2c5? > Why not add "bootph-pre-ram;" for them? Would they be needed before relocation of U-Boot to DRAM? Best regards Heinrich