From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932832AbcGIAD2 (ORCPT ); Fri, 8 Jul 2016 20:03:28 -0400 Received: from mail.savoirfairelinux.com ([208.88.110.44]:43560 "EHLO mail.savoirfairelinux.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756290AbcGIADT (ORCPT ); Fri, 8 Jul 2016 20:03:19 -0400 Date: Fri, 8 Jul 2016 20:03:15 -0400 (EDT) From: Vivien Didelot To: Andrew Lunn Cc: netdev , linux-kernel , kernel , David , Florian Fainelli Message-ID: <2075477569.472619.1468022595798.JavaMail.zimbra@savoirfairelinux.com> In-Reply-To: <20160707135253.GO19800@lunn.ch> References: <20160707125758.1547-1-vivien.didelot@savoirfairelinux.com> <20160707125758.1547-7-vivien.didelot@savoirfairelinux.com> <20160707135253.GO19800@lunn.ch> Subject: Re: [PATCH net-next 6/9] net: dsa: mv88e6xxx: rework Switch MAC setter MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Mailer: Zimbra 8.6.0_GA_1153 (ZimbraWebClient - FF47 (Linux)/8.6.0_GA_1153) Thread-Topic: mv88e6xxx: rework Switch MAC setter Thread-Index: 4NRASigoAPy8U1wgBfRYVkqD4lqT5Q== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andrew, On Jul 7, 2016, at 9:52 AM, Andrew Lunn andrew@lunn.ch wrote: >> Also, note that this indirect access is a single-register which doesn't >> require to wait for the operation to complete (like Switch MAC, Trunk >> Mapping, etc.), in contrary to multi-registers indirect accesses with >> several busy operations (like ATU, VTU, etc.). > > Are you sure about this? The DSDT polls bit 15 of the register. Every single-register operation (with an "Update" bit, "pointer" and "data" bits) execute in a single write operation and doesn't need to wait for completion. But multiple-register operations like ATU, VTU, etc. with a "Busy" bit, Operation bits and data registers, do require and explicitly mention to wait for the operation to complete (by polling the busy bit or via interrupt). We could add checks but it doesn't sound necessary, we are not doing it for others Update operations and a badly set switch MAC address would be easily identifiable. Thanks, Vivien