From: Jon Hunter <jonathanh@nvidia.com>
To: Prathamesh Shete <pshete@nvidia.com>,
linusw@kernel.org, brgl@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, thierry.reding@gmail.com, robh@kernel.org,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/3] arm64: tegra: Add Tegra264 GPIO controllers
Date: Fri, 23 Jan 2026 09:29:23 +0000 [thread overview]
Message-ID: <20c30d15-fc36-4db5-bdb2-30f8a45f9cf3@nvidia.com> (raw)
In-Reply-To: <20260123064140.1095946-3-pshete@nvidia.com>
On 23/01/2026 06:41, Prathamesh Shete wrote:
> Add device tree nodes for MAIN, AON and UPHY GPIO controller instances.
>
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> ---
> Changes in v2:
> * Update Tegra264 GPIO nodes to use “wakeup-parent”.
> ---
> arch/arm64/boot/dts/nvidia/tegra264.dtsi | 88 ++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index f137565da804..cf4de2c517fa 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -3277,6 +3277,50 @@
> status = "disabled";
> };
>
> + gpio_main: gpio@c300000 {
> + compatible = "nvidia,tegra264-gpio";
> + reg = <0x00 0x0c300000 0x0 0x4000>,
> + <0x00 0x0c310000 0x0 0x4000>;
> + reg-names = "security", "gpio";
> + wakeup-parent = <&pmc>;
> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> serial@c4e0000 {
> compatible = "nvidia,tegra264-utc";
> reg = <0x0 0x0c4e0000 0x0 0x8000>,
> @@ -3347,6 +3391,22 @@
> #interrupt-cells = <2>;
> interrupt-controller;
> };
> +
> + gpio_aon: gpio@cf00000 {
> + compatible = "nvidia,tegra264-gpio-aon";
> + reg = <0x0 0x0cf00000 0x0 0x10000>,
> + <0x0 0x0cf10000 0x0 0x1000>;
> + reg-names = "security", "gpio";
> + wakeup-parent = <&pmc>;
> + interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> };
>
> /* TOP_MMIO */
> @@ -3726,6 +3786,34 @@
>
> ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */
> <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */
> +
> + gpio_uphy: gpio@8300000 {
> + compatible = "nvidia,tegra264-gpio-uphy";
> + reg = <0x00 0x08300000 0x0 0x2000>,
> + <0x00 0x08310000 0x0 0x2000>;
> + reg-names = "security", "gpio";
> + wakeup-parent = <&pmc>;
> + interrupts = <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> };
>
> cpus {
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Thanks!
Jon
--
nvpublic
next prev parent reply other threads:[~2026-01-23 9:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-23 6:41 [PATCH v2 1/3] dt-bindings: gpio: Add Tegra264 support Prathamesh Shete
2026-01-23 6:41 ` [PATCH v2 2/3] gpio: tegra186: Add support for Tegra264 Prathamesh Shete
2026-01-23 9:28 ` Jon Hunter
2026-01-23 6:41 ` [PATCH v2 3/3] arm64: tegra: Add Tegra264 GPIO controllers Prathamesh Shete
2026-01-23 9:29 ` Jon Hunter [this message]
2026-01-23 9:04 ` [PATCH v2 1/3] dt-bindings: gpio: Add Tegra264 support Krzysztof Kozlowski
2026-01-23 9:51 Prathamesh Shete
2026-01-23 9:51 ` [PATCH v2 3/3] arm64: tegra: Add Tegra264 GPIO controllers Prathamesh Shete
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