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d=pengutronix.de; s=20260414; t=1792052741; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wrxfajdvFmJtNiWzGN9eypZ6XVjairWUkY35gVPYWFY=; b=VHChhYmOypm0trb/T3G7ioVgQB3Gk+9RkxCOM9hSbJmABlyKnlJMMyZLA286oOH02dFZiM MAsPWPd2+Et6AaLPnrNWgnZqHb5Ohsdk5U9avr5zPYn6GJxjHxxmN2+dbpeO7CA4tFVF8l Y70B0Ol3E/3iBb4CjXW8Xje6tITRAsonYInrkW9ZRcMmJX1LGj0iIca/LBkG0K2rMzp7pp ch7IR3aTtYf8GiVhCFrT6Ldw6m3Lzr5nJ4m1/PBcopUBYeHHmmbJQ29/rgURvxl+KLfVyv TxUUA7+qW9x0jA9rnDvti6tAfSG+bAhx6v3kqD3qbjN3gj50L+iLTFt5GjK+fA== Message-ID: <20cc437c1e95aca578ac814c2e0f4f0f3ddd71d4.camel@pengutronix.de> Subject: Re: [PATCH v6 09/10] PCI: dw-rockchip: Add system PM support From: Philipp Zabel To: Sebastian Reichel , Lorenzo Pieralisi , Krzysztof =?UTF-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Date: Thu, 15 Oct 2026 10:25:40 +0200 In-Reply-To: <20260908-rockchip-pcie-system-suspend-v6-9-fbabcca9921b@collabora.com> References: <20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com> <20260908-rockchip-pcie-system-suspend-v6-9-fbabcca9921b@collabora.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-0+deb13u1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Di, 2026-09-08 at 16:51 +0200, Sebastian Reichel wrote: > Add system PM support for Rockchip PCIe Designware Controllers. >=20 > I've tested this on the Rockchip RK3576 EVB1, the Radxa ROCK 4D > and the ArmSom Sige5 boards. >=20 > While I haven't experienced any issues, most of my tests have been done > without any devices attached (i.e. default board without any extras), so > there _might_ still be some problems. As system suspend does not work at > all right now, I think it makes sense to get at least the basic > configurations working as soon as possible as it will allow us to catch > regressions by enabling system suspend in CI systems like KernelCI. >=20 > Co-developed-by: Shawn Lin > Signed-off-by: Shawn Lin > Signed-off-by: Sebastian Reichel > --- > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 100 ++++++++++++++++++++= ++++++ > 1 file changed, 100 insertions(+) >=20 > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/= controller/dwc/pcie-dw-rockchip.c > index 47d9cab909bc..e675918ba184 100644 > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -120,6 +120,7 @@ struct rockchip_pcie { [...] > +static int rockchip_pcie_resume(struct device *dev) > +{ > + struct rockchip_pcie *rockchip =3D dev_get_drvdata(dev); > + struct dw_pcie *pci =3D &rockchip->pci; > + int ret; > + > + if (rockchip->data->mode =3D=3D DW_PCIE_EP_TYPE) { > + dev_err(dev, "resume is not supported in EP mode\n"); > + return -EOPNOTSUPP; > + } > + > + ret =3D clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks); > + if (ret) { > + dev_err(dev, "clock init failed: %d\n", ret); > + return ret; > + } > + > + if (rockchip->vpcie3v3) { > + ret =3D regulator_enable(rockchip->vpcie3v3); > + if (ret) > + goto err_disable_clk; > + } > + > + ret =3D rockchip_pcie_phy_init(rockchip); > + if (ret) { > + dev_err(dev, "phy init failed: %d\n", ret); > + goto err_disable_regulator; > + } > + > + reset_control_deassert(rockchip->rst); Missing error handling. This is inconsistent with the existing calls in rockchip_pcie_probe() and rockchip_pcie_rc_reset_root_port(). regards Philipp