From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224MHnDe81jUgiMGXO/9PGZNrr+3EwjD2ljoj+s5Ip/MVgtkTBHSRZVAafcFdVeRuEbOiE5O ARC-Seal: i=1; a=rsa-sha256; t=1516541270; cv=none; d=google.com; s=arc-20160816; b=ULsRaHHu/94+x9+Degba4lM1o7/9Yap0vq/FCeHgOjkKapuct4trQHOjUViCrf5zL6 oChsjsm9b+v2V+lG0/0PSDLW2IZiM8CGaZGuvoNwAh/nU1MINQ6VRvH2t8qDaZHaCu53 YRGKeL7k8HMxCsWns3pQnsqznZaVhl+9h9Gc5EHRQC2a0mB8Dv8ZjsDHICRULYiF0AgD R2T22XpV4E0qtljf4axVxc/3n022nA6L2ItW26WXN2VWq5D5cCOwSq9xiAO30/WaslRF Cfe9GWGdKOnACz/OUUS3EhJ+jx3Sc5jwqCxORRKtw3zimrbLGoO8i0UYTNKo55wirD7n l8Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=importance:content-transfer-encoding:mime-version:user-agent:cc:to :from:subject:date:references:in-reply-to:message-id:dkim-signature :arc-authentication-results; bh=w+1sVOSCt/ga3aPFrB72z+VsE94wYtFoDWwm1mJ7+0A=; b=kNtWPllmSfts9wGBqHWzgnP86zTxa6yLRhAPMlCvsxbpby/Glt04sXLEve+8hJ/yiE N21bmg0gLGVNtkHmE9ztEzCe3r0ZfT0r+bYdpIlfN/WrZcCYlxo5d/BCVhmc7mCdmC5w x3Nbc7X99/uPrIeLk9Cg9Vq24gCzZZh4O7IeyT1aop1qDvdgt03qIjbzjvaWrYSgP1LR 94ZtZpt5V1NaNhI9OUO7rp/TChzwHO5/OEQ5LiACieSa88aFacMEyP2Gwpjjp7kjBd1a FxE0KWTX1vBcpWihzZ97phxFWjSHwrEIc+0EZjJRf51DmY1EVnyf8uZ5JllVDg1IzUiE 6yBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@infradead.org header.s=twosheds.20170209 header.b=vub9PQuP; spf=pass (google.com: best guess record for domain of batv+c3727a9e9cf4ad240057+5264+infradead.org+dwmw2@twosheds.srs.infradead.org designates 2001:8b0:10b:1:21d:7dff:fe04:dbe2 as permitted sender) smtp.mailfrom=BATV+c3727a9e9cf4ad240057+5264+infradead.org+dwmw2@twosheds.srs.infradead.org Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=twosheds.20170209 header.b=vub9PQuP; spf=pass (google.com: best guess record for domain of batv+c3727a9e9cf4ad240057+5264+infradead.org+dwmw2@twosheds.srs.infradead.org designates 2001:8b0:10b:1:21d:7dff:fe04:dbe2 as permitted sender) smtp.mailfrom=BATV+c3727a9e9cf4ad240057+5264+infradead.org+dwmw2@twosheds.srs.infradead.org Message-ID: <2100854a140a0758f4e0c70e80e22701.squirrel@twosheds.infradead.org> In-Reply-To: References: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> <1516528149-9370-4-git-send-email-dwmw@amazon.co.uk> Date: Sun, 21 Jan 2018 13:27:30 -0000 Subject: Re: [PATCH v2 3/8] x86/msr: Add definitions for new speculation control MSRs From: "David Woodhouse" To: "Jiri Slaby" Cc: "David Woodhouse" , arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org User-Agent: SquirrelMail/1.4.22-21.fc27 MIME-Version: 1.0 Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: 8bit X-Priority: 3 (Normal) Importance: Normal X-SRS-Rewrite: SMTP reverse-path rewritten from by twosheds.infradead.org. See http://www.infradead.org/rpr.html X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590195051986587278?= X-GMAIL-MSGID: =?utf-8?q?1590208775933980767?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: > On 01/21/2018, 10:49 AM, David Woodhouse wrote: >> Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and >> ARCH_CAPABILITIES. >> >> See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf >> >> Signed-off-by: David Woodhouse >> --- >> arch/x86/include/asm/msr-index.h | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/arch/x86/include/asm/msr-index.h >> b/arch/x86/include/asm/msr-index.h >> index fa11fb1..3e50463 100644 >> --- a/arch/x86/include/asm/msr-index.h >> +++ b/arch/x86/include/asm/msr-index.h >> @@ -42,6 +42,13 @@ >> #define MSR_PPIN_CTL 0x0000004e >> #define MSR_PPIN 0x0000004f >> >> +#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ >> +#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted >> Speculation */ >> +#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch >> Predictors */ >> + >> +#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ >> +#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction >> Barrier */ >> + >> #define MSR_IA32_PERFCTR0 0x000000c1 >> #define MSR_IA32_PERFCTR1 0x000000c2 >> #define MSR_FSB_FREQ 0x000000cd >> @@ -60,6 +67,10 @@ >> #define MSR_IA32_BBL_CR_CTL 0x00000119 >> #define MSR_IA32_BBL_CR_CTL3 0x0000011e >> >> +#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a >> +#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ >> +#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ > > Is there any reason why all 3 are not properly sorted? > 0x04e > 0x048 > 0x119 > 0x10a Er... no good reason. I was definitely *trying* to put them in the right place. I plead incompetence; will fix... -- dwmw2