From: Markus Elfring <Markus.Elfring@web.de>
To: Himanshu Mittal <h-mittal1@ti.com>,
netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: LKML <linux-kernel@vger.kernel.org>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
MD Danish Anwar <danishanwar@ti.com>,
Meghana Malladi <m-malladi@ti.com>,
Paolo Abeni <pabeni@redhat.com>,
prajith@ti.com, Pratheesh Gangadhar <pratheesh@ti.com>,
Simon Horman <horms@kernel.org>, Sriramakrishnan <srk@ti.com>,
Roger Quadros <rogerq@kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>
Subject: Re: [PATCH net v2] net: ti: icssg-prueth: Fix buffer allocation for ICSSG
Date: Thu, 17 Jul 2025 14:18:53 +0200 [thread overview]
Message-ID: <21104b21-c24f-4b1f-bd6e-072597927e81@web.de> (raw)
In-Reply-To: <20250710131250.1294278-1-h-mittal1@ti.com>
…
> +++ b/drivers/net/ethernet/ti/icssg/icssg_config.c
> @@ -288,8 +288,12 @@ static int prueth_fw_offload_buffer_setup(struct prueth_emac *emac)
> int i;
>
> addr = lower_32_bits(prueth->msmcram.pa);
> - if (slice)
> - addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE;
> + if (slice) {
> + if (prueth->pdata.banked_ms_ram)
> + addr += MSMC_RAM_BANK_SIZE;
> + else
> + addr += PRUETH_SW_TOTAL_BUF_SIZE_PER_SLICE;
> + }
…
How do you think about to use the following code variant?
if (slice)
addr += ( prueth->pdata.banked_ms_ram
? MSMC_RAM_BANK_SIZE
: PRUETH_SW_TOTAL_BUF_SIZE_PER_SLICE);
Regards,
Markus
prev parent reply other threads:[~2025-07-17 12:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-10 13:12 Himanshu Mittal
2025-07-11 14:43 ` Simon Horman
2025-07-15 7:07 ` MITTAL, HIMANSHU
2025-07-15 10:29 ` Simon Horman
2025-07-17 9:37 ` MITTAL, HIMANSHU
2025-07-17 12:18 ` Markus Elfring [this message]
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