From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m49195.qiye.163.com (mail-m49195.qiye.163.com [45.254.49.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CB5B33CE80 for ; Mon, 1 Jun 2026 10:50:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780311016; cv=none; b=fVy0jZ2DeGbijK8TIrzxyjClZ4hqqwByQbLspkSV3WcZ5W8cNtmxGPAiaiJvDSpucX7x3zTBZicBQn6q4D1H6KI3XzKRD7PqaOqmG5mN0m3zOl0u/VB5tphbwTszcz+RPqZomhzZuVa/b/szEPtCTyoV7mC42vaHpO67hrKPuvs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780311016; c=relaxed/simple; bh=w4ZFzPXp6SaZtzMBiJupUAJLinbTLIQATAQHQ6kkjms=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=qnsb3+a/m+lZTfitZxbshWNI6o3rhgY+lxkwUKEKEFZL/3n1dsSgZSn9k9cq9lEKh6k7pcZrd77MLHVJtuHCCKOnPVqTecybTU2Dh6IR9fp2MYJp9mw9bkkp/ty4dYZOB4iv0tWMNdzVv/+BR2fFcLKOV6yGKte/kJe0G8p2xts= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=MIFkC8AH; arc=none smtp.client-ip=45.254.49.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="MIFkC8AH" Received: from [172.16.12.77] (unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 40978354e; Mon, 1 Jun 2026 18:44:55 +0800 (GMT+08:00) Message-ID: <2111c699-bf61-4451-b33b-a848b166eb9e@rock-chips.com> Date: Mon, 1 Jun 2026 18:44:38 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] drm/rockchip: vop2: Fix wrong wait target in layer cfg done check To: Cristian Ciocaltea , Sandy Huang , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260504-vop2-layer-cfg-tmout-v1-0-730226a7331e@collabora.com> <20260504-vop2-layer-cfg-tmout-v1-1-730226a7331e@collabora.com> Content-Language: en-US From: Andy Yan In-Reply-To: <20260504-vop2-layer-cfg-tmout-v1-1-730226a7331e@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-HM-Tid: 0a9e82c95da409d8kunm01c27a9638cd97 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkaSUJIVh9LSkpNQh4aT0JIGFYVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU 9PT0hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=MIFkC8AHwHL2FWUnQEEtZJFPzaWQekHV6xdH/eKwuXwzxG04rty0Z9H/P4M4t7pUMQgPv9cLtRLyZ6RMo5iTCWLUB33uiKRDddJ5guMQnJsxRBgqHO/Z9YqbmTuKFNICGYMvmH9s01O+hD9Zt93girlwQj/BAoExeRLjDfYJYRI=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=k6cFF0rW3WqjUdNa0VXwx7EfaVYwhaHvZBGWXQyCUWY=; h=date:mime-version:subject:message-id:from; Hello, On 5/5/26 02:23, Cristian Ciocaltea wrote: > rk3568_vop2_setup_layer_mixer() waits for the previous Video Port (VP) > layer configuration to take effect before writing a new one to the > shared RK3568_OVL_LAYER_SEL shadow register. However, it passes > vop2->old_layer_sel to rk3568_vop2_wait_for_layer_cfg_done() as the > expected value, which at that point already contains the new VP layer. > > This causes the wait to poll for a value that has not been written to > the shadow register yet, resulting in spurious timeouts when two > non-blocking atomic commits race: > > rockchip-drm display-subsystem: [drm] *ERROR* wait layer cfg done timeout [...] > > Pass the local old_layer_sel instead, which still holds the value > captured from vop2->old_layer_sel before it was overwritten, i.e. the > previous VP target that the hardware is expected to latch. > > Fixes: 3e89a8c68354 ("drm/rockchip: vop2: Fix the update of LAYER/PORT select registers when there are multi display output on rk3588/rk3568") > Signed-off-by: Cristian Ciocaltea Reviewed-by: Andy Yan > --- > drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c > index 02a788a4dfdd..edca0fb16e08 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c > @@ -2307,7 +2307,7 @@ static void rk3568_vop2_setup_layer_mixer(struct vop2_video_port *vp) > * Changes of other VPs' overlays have not taken effect > */ > if (cfg_done) > - rk3568_vop2_wait_for_layer_cfg_done(vop2, vop2->old_layer_sel); > + rk3568_vop2_wait_for_layer_cfg_done(vop2, old_layer_sel); > } > > vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); >