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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Russell King , Andrew Lunn , Heiner Kallweit , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Martin Kaistra , Benedikt Spranger Date: Wed, 30 Sep 2026 16:00:56 +0200 In-Reply-To: References: <20260923-devel-vstrassheim-soce-dsa-ml-v3-0-ddebafcb9ba7@linutronix.de> <20260923-devel-vstrassheim-soce-dsa-ml-v3-2-ddebafcb9ba7@linutronix.de> Organization: Linutronix GmbH Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Sat, 2026-09-26 at 00:55 +0200, Andrew Lunn wrote: > > The controller exposes separate register regions for transaction data > > and for the shared transaction control and external bus selector > > register. >=20 > > +examples: > > + - | > > + mdio@204 { > > + compatible =3D "soce,swip-mdio-23-02"; > > + reg =3D <0x204 0xc>, <0x200 0x4>; >=20 > At least in the example, they are not separate? Not separate regions but registers... I'm obviously bad at documenting things. The current information in the commit message is misleading and irrelevant. Looking at the bot's feedback, it's at the same time not clear enough yet that the mdio controller part is mapped within the switch memory and can't be used separately from it. I will update the commit message to something like this: Add a binding for the MDIO controller integrated into SoC-e SWIP Ethernet switch IP cores. The controller shares the memory of the synthesized switch IP core and cannot be used independently. >=20 > =C2=A0=C2=A0=C2=A0Andrew Thanks, Vasilij