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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5c0087ddd18sm270965e87.21.2026.11.06.13.38.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Nov 2026 13:38:43 -0800 (PST) Message-ID: <21be3761-9da9-48c6-aaa1-b56f8625167a@linaro.org> Date: Fri, 6 Nov 2026 23:38:42 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/7] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS To: mail@andrewgigena.dev, Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Mauro Carvalho Chehab , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Andi Shyti , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org References: <20261106-sm8150-v7.4-rc1-camss-v3-0-0103e8a0bbcd@andrewgigena.dev> <20261106-sm8150-v7.4-rc1-camss-v3-2-0103e8a0bbcd@andrewgigena.dev> From: Vladimir Zapolskiy In-Reply-To: <20261106-sm8150-v7.4-rc1-camss-v3-2-0103e8a0bbcd@andrewgigena.dev> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/6/26 20:35, Andrew Gigena via B4 Relay wrote: > From: Andrew Gigena > > Document the Qualcomm SM8150 Camera Subsystem. The IP integrates four > CSIPHY, four CSID (two full and two lite), two VFE and two VFE-Lite > instances, with 19 clocks, 8 interrupts, eight IOMMU streams, four > interconnect paths and three power domains. > > The CSIPHY I/O spaces are not part of the CAMSS container device: each > CSIPHY is driven by the dedicated qcom,sm8150-csi2-phy driver, so this > binding only describes the VFE and CSID resources. Each CSI input port > is described with data lanes starting at 1, as required by the CAMSS > PHY mode. > > Describe SM8150 in a dedicated schema instead of reusing another SoC's > schema. > > Signed-off-by: Andrew Gigena > --- > .../bindings/media/qcom,sm8150-camss.yaml | 285 +++++++++++++++++++++ > 1 file changed, 285 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml > new file mode 100644 > index 000000000000..371ff1ce0bd2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml > @@ -0,0 +1,285 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sm8150-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8150 Camera Subsystem (CAMSS) > + > +maintainers: > + - Andrew Gigena > + > +description: > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,sm8150-camss > + > + reg: > + maxItems: 8 > + > + reg-names: > + items: > + - const: vfe0 > + - const: csid0 > + - const: vfe1 > + - const: csid1 > + - const: vfe_lite0 > + - const: csid_lite0 > + - const: vfe_lite1 > + - const: csid_lite1 That's an intermix of names, and you will get a review comment from Krzysztof about it, I stand aside. > + > + clocks: > + maxItems: 19 > + > + clock-names: > + items: > + - const: camnoc_axi > + - const: cpas_ahb > + - const: vfe0_axi > + - const: vfe0 > + - const: vfe0_cphy_rx > + - const: vfe0_csid > + - const: vfe1_axi > + - const: vfe1 > + - const: vfe1_cphy_rx > + - const: vfe1_csid > + - const: vfe_lite0 > + - const: vfe_lite0_cphy_rx > + - const: vfe_lite0_csid > + - const: vfe_lite1 > + - const: vfe_lite1_cphy_rx > + - const: vfe_lite1_csid > + - const: gcc_ahb > + - const: gcc_axi_hf > + - const: gcc_axi_sf Drop 'gcc_axi_sf'. > + > + interrupts: > + maxItems: 8 > + > + interrupt-names: > + items: > + - const: vfe0 > + - const: csid0 > + - const: vfe1 > + - const: csid1 > + - const: vfe_lite0 > + - const: csid_lite0 > + - const: vfe_lite1 > + - const: csid_lite1 Here too. > + > + interconnects: > + maxItems: 4 > + > + interconnect-names: > + items: > + - const: cam_ahb > + - const: cam_hf_0_mnoc > + - const: cam_sf_0_mnoc > + - const: cam_hf_1_mnoc Drop 'cam_' prefix and 'cam_sf_0_mnoc' also. > + > + iommus: > + maxItems: 8 > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domain-names: > + items: > + - const: ife0 > + - const: ife1 > + - const: top > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports, one per CSI2 PHY instance. > + > + patternProperties: > + "^port@[0-3]$": > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + > + description: > + Input port for receiving CSI data from a CSIPHY. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + items: > + minimum: 1 > + maximum: 4 > + > + bus-type: > + enum: > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY Or C-PHY, right?.. In fact you shall drop bus-type from here, because the link between CAMSS and PHY's output is not a CSI-2 bus, it makes it inapplicable. 'bus-type' is needed only between CSIPHY and a sensor connected to it. > + > + required: > + - data-lanes > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - interconnects > + - interconnect-names > + - interrupts > + - interrupt-names > + - iommus > + - power-domains > + - power-domain-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + isp@acaf000 { > + compatible = "qcom,sm8150-camss"; > + > + reg = <0 0xacaf000 0 0x4000>, > + <0 0xacb3000 0 0x1000>, > + <0 0xacb6000 0 0x4000>, > + <0 0xacba000 0 0x1000>, > + <0 0xacc4000 0 0x4000>, > + <0 0xacc8000 0 0x1000>, > + <0 0xaccb000 0 0x4000>, > + <0 0xaccf000 0 0x1000>; > + > + reg-names = "vfe0", > + "csid0", > + "vfe1", > + "csid1", > + "vfe_lite0", > + "csid_lite0", > + "vfe_lite1", > + "csid_lite1"; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_IFE_0_AXI_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_0_CSID_CLK>, > + <&camcc CAM_CC_IFE_1_AXI_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_1_CSID_CLK>, > + <&camcc CAM_CC_IFE_LITE_0_CLK>, > + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, > + <&camcc CAM_CC_IFE_LITE_1_CLK>, > + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>, > + <&gcc GCC_CAMERA_AHB_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>; > + > + clock-names = "camnoc_axi", > + "cpas_ahb", > + "vfe0_axi", > + "vfe0", > + "vfe0_cphy_rx", > + "vfe0_csid", > + "vfe1_axi", > + "vfe1", > + "vfe1_cphy_rx", > + "vfe1_csid", > + "vfe_lite0", > + "vfe_lite0_cphy_rx", > + "vfe_lite0_csid", > + "vfe_lite1", > + "vfe_lite1_cphy_rx", > + "vfe_lite1_csid", > + "gcc_ahb", > + "gcc_axi_hf", > + "gcc_axi_sf"; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + > + interrupt-names = "vfe0", > + "csid0", > + "vfe1", > + "csid1", > + "vfe_lite0", > + "csid_lite0", > + "vfe_lite1", > + "csid_lite1"; > + > + power-domains = <&camcc IFE_0_GDSC>, > + <&camcc IFE_1_GDSC>, > + <&camcc TITAN_TOP_GDSC>; > + > + power-domain-names = "ife0", > + "ife1", > + "top"; > + > + interconnects = <&gem_noc MASTER_AMPSS_M0 0 > + &config_noc SLAVE_CAMERA_CFG 0>, > + <&mmss_noc MASTER_CAMNOC_HF0 0 > + &mc_virt SLAVE_EBI_CH0 0>, > + <&mmss_noc MASTER_CAMNOC_SF 0 > + &mc_virt SLAVE_EBI_CH0 0>, > + <&mmss_noc MASTER_CAMNOC_HF1 0 > + &mc_virt SLAVE_EBI_CH0 0>; > + > + interconnect-names = "cam_ahb", > + "cam_hf_0_mnoc", > + "cam_sf_0_mnoc", > + "cam_hf_1_mnoc"; > + > + iommus = <&apps_smmu 0x840 0x620>, > + <&apps_smmu 0x860 0x620>, > + <&apps_smmu 0xa40 0x620>, > + <&apps_smmu 0xa60 0x620>, > + <&apps_smmu 0xc40 0x620>, > + <&apps_smmu 0xc60 0x620>, > + <&apps_smmu 0xe40 0x620>, > + <&apps_smmu 0xe60 0x620>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + endpoint { > + bus-type = ; > + data-lanes = <1 2 3 4>; > + remote-endpoint = <&csiphy0_out>; > + }; > + }; > + }; > + }; > + }; > -- Best wishes, Vladimir