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Thu, 7 May 2020 07:46:02 +0000 (UTC) Received: from [10.36.114.214] (ovpn-114-214.ams2.redhat.com [10.36.114.214]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 47DEB5C1B0; Thu, 7 May 2020 07:45:52 +0000 (UTC) Subject: Re: [PATCH v11 00/13] SMMUv3 Nested Stage Setup (IOMMU part) To: Shameerali Kolothum Thodi , Zhangfei Gao , "eric.auger.pro@gmail.com" , "iommu@lists.linux-foundation.org" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "kvmarm@lists.cs.columbia.edu" , "will@kernel.org" , "joro@8bytes.org" , "maz@kernel.org" , "robin.murphy@arm.com" Cc: "jean-philippe@linaro.org" , "alex.williamson@redhat.com" , "jacob.jun.pan@linux.intel.com" , "yi.l.liu@intel.com" , "peter.maydell@linaro.org" , "tn@semihalf.com" , "bbhushan2@marvell.com" References: <20200414150607.28488-1-eric.auger@redhat.com> <06fe02f7-2556-8986-2f1e-dcdf59773b8c@redhat.com> From: Auger Eric Message-ID: <21e162a0-b29f-94a4-8371-7e3ac2743539@redhat.com> Date: Thu, 7 May 2020 09:45:51 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Shameer, On 5/7/20 8:59 AM, Shameerali Kolothum Thodi wrote: > Hi Eric, >=20 >> -----Original Message----- >> From: Shameerali Kolothum Thodi >> Sent: 30 April 2020 10:38 >> To: 'Auger Eric' ; Zhangfei Gao >> ; eric.auger.pro@gmail.com; >> iommu@lists.linux-foundation.org; linux-kernel@vger.kernel.org; >> kvm@vger.kernel.org; kvmarm@lists.cs.columbia.edu; will@kernel.org; >> joro@8bytes.org; maz@kernel.org; robin.murphy@arm.com >> Cc: jean-philippe@linaro.org; alex.williamson@redhat.com; >> jacob.jun.pan@linux.intel.com; yi.l.liu@intel.com; peter.maydell@linar= o.org; >> tn@semihalf.com; bbhushan2@marvell.com >> Subject: RE: [PATCH v11 00/13] SMMUv3 Nested Stage Setup (IOMMU part) >> >> Hi Eric, >> >>> -----Original Message----- >>> From: Auger Eric [mailto:eric.auger@redhat.com] >>> Sent: 16 April 2020 08:45 >>> To: Zhangfei Gao ; eric.auger.pro@gmail.com; >>> iommu@lists.linux-foundation.org; linux-kernel@vger.kernel.org; >>> kvm@vger.kernel.org; kvmarm@lists.cs.columbia.edu; will@kernel.org; >>> joro@8bytes.org; maz@kernel.org; robin.murphy@arm.com >>> Cc: jean-philippe@linaro.org; Shameerali Kolothum Thodi >>> ; alex.williamson@redhat.com; >>> jacob.jun.pan@linux.intel.com; yi.l.liu@intel.com; peter.maydell@lina= ro.org; >>> tn@semihalf.com; bbhushan2@marvell.com >>> Subject: Re: [PATCH v11 00/13] SMMUv3 Nested Stage Setup (IOMMU part) >>> >>> Hi Zhangfei, >>> >>> On 4/16/20 6:25 AM, Zhangfei Gao wrote: >>>> >>>> >>>> On 2020/4/14 =E4=B8=8B=E5=8D=8811:05, Eric Auger wrote: >>>>> This version fixes an issue observed by Shameer on an SMMU 3.2, >>>>> when moving from dual stage config to stage 1 only config. >>>>> The 2 high 64b of the STE now get reset. Otherwise, leaving the >>>>> S2TTB set may cause a C_BAD_STE error. >>>>> >>>>> This series can be found at: >>>>> https://github.com/eauger/linux/tree/v5.6-2stage-v11_10.1 >>>>> (including the VFIO part) >>>>> The QEMU fellow series still can be found at: >>>>> https://github.com/eauger/qemu/tree/v4.2.0-2stage-rfcv6 >>>>> >>>>> Users have expressed interest in that work and tested v9/v10: >>>>> - https://patchwork.kernel.org/cover/11039995/#23012381 >>>>> - https://patchwork.kernel.org/cover/11039995/#23197235 >>>>> >>>>> Background: >>>>> >>>>> This series brings the IOMMU part of HW nested paging support >>>>> in the SMMUv3. The VFIO part is submitted separately. >>>>> >>>>> The IOMMU API is extended to support 2 new API functionalities: >>>>> 1) pass the guest stage 1 configuration >>>>> 2) pass stage 1 MSI bindings >>>>> >>>>> Then those capabilities gets implemented in the SMMUv3 driver. >>>>> >>>>> The virtualizer passes information through the VFIO user API >>>>> which cascades them to the iommu subsystem. This allows the guest >>>>> to own stage 1 tables and context descriptors (so-called PASID >>>>> table) while the host owns stage 2 tables and main configuration >>>>> structures (STE). >>>>> >>>>> >>>> >>>> Thanks Eric >>>> >>>> Tested v11 on Hisilicon kunpeng920 board via hardware zip accelerato= r. >>>> 1. no-sva works, where guest app directly use physical address via i= octl. >>> Thank you for the testing. Glad it works for you. >>>> 2. vSVA still not work, same as v10, >>> Yes that's normal this series is not meant to support vSVM at this st= age. >>> >>> I intend to add the missing pieces during the next weeks. >> >> Thanks for that. I have made an attempt to add the vSVA based on >> your v10 + JPBs sva patches. The host kernel and Qemu changes can >> be found here[1][2]. >> >> This basically adds multiple pasid support on top of your changes. >> I have done some basic sanity testing and we have some initial success >> with the zip vf dev on our D06 platform. Please note that the STALL ev= ent is >> not yet supported though, but works fine if we mlock() guest usr mem. >=20 > I have added STALL support for our vSVA prototype and it seems to be > working(on our hardware). I have updated the kernel and qemu branches w= ith > the same[1][2]. I should warn you though that these are prototype code = and I am pretty > much re-using the VFIO_IOMMU_SET_PASID_TABLE interface for almost every= thing. > But thought of sharing, in case if it is useful somehow!. Thank you very much for your work. I intend to look at your additions by beginning of next week. Best Regards Eric >=20 > Thanks, > Shameer >=20 > [1]https://github.com/hisilicon/kernel-dev/commits/vsva-prototype-host-= v1 >=20 > [2]https://github.com/hisilicon/qemu/tree/v4.2.0-2stage-rfcv6-vsva-prot= otype-v1 >=20