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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c16609e627sm205631375ad.52.2026.06.08.23.27.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 23:27:42 -0700 (PDT) Message-ID: <21e5e1ee-c083-43a2-9f66-cdd07b529111@oss.qualcomm.com> Date: Tue, 9 Jun 2026 14:27:37 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 07/15] drm/msm/dp: move the pixel clock control to its own API To: Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar , Dmitry Baryshkov References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> <20260602-dp_mstclean-v6-7-2c17ff40a9b2@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=H+DrBeYi c=1 sm=1 tr=0 ts=6a27b260 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=iRcVBvsBG4cgb8Ug3_IA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA5MDA1OCBTYWx0ZWRfX2zU16rfUbSMm XSeb/fPX17HrO1N5JZQosrosCE2MDEa5AxECBPCL7T3gAWfBlPON9CuZUgAC4nOu/GmZa0caDay UUItz27g5jpC0PAJ8o47pC9aZAIrgLGdvn+QUV5oQw9lZf/4R8KN/epWtmlny+jvXovV1nv0Cf0 HWsOcqWjOzv0RwMgzwKbRasC9O5AaWnV+w1Tutu92sXtAjouJW2kxBtRyFMV68laoXs3d+aYvhY L2wMdWcYH1vmtV6lGuUAe5Gu8W1o8ttLg99B15CJFp1/lWdGiE97Yf4DJBWaJmioy82w+0MLvaP 6Y1MhFxBAJjAXh0G5mbMwyTvCOOh6N3bbM62gdJqImEgi292PJF3JtRJjTuhjKDZIxeXAO9qVHQ 5YrtIioRyLoh96AWFsOcocpOlnepZr+RdxD9EAwmlXbtj4xkr2IyhxtizVXCXRl2KI18jFzQWSV gxY2gsCucYlfWJp3U4w== X-Proofpoint-ORIG-GUID: TyNDlx93Uh4WTGavmBXT3moH_gY2PgYM X-Proofpoint-GUID: TyNDlx93Uh4WTGavmBXT3moH_gY2PgYM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-09_01,2026-06-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606090058 On 6/8/2026 3:43 PM, Konrad Dybcio wrote: > On 6/2/26 11:11 AM, Yongxing Mou wrote: >> Enable/Disable of DP pixel clock happens in multiple code paths >> leading to code duplication. Move it into individual helpers so that >> the helpers can be called wherever necessary. >> >> Signed-off-by: Abhinav Kumar >> Signed-off-by: Yongxing Mou >> Reviewed-by: Dmitry Baryshkov >> --- >> drivers/gpu/drm/msm/dp/dp_ctrl.c | 81 +++++++++++++++++++++------------------- >> 1 file changed, 42 insertions(+), 39 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> index 1c2eccec6ec6..ac0a2c387f03 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c >> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> @@ -2171,6 +2171,42 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) >> return success; >> } >> >> +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate) >> +{ >> + int ret; >> + >> + ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); >> + if (ret) { >> + DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); >> + return ret; >> + } >> + >> + if (ctrl->stream_clks_on) { >> + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); > > if (WARN_ON_ONCE(ctrl->stream_clks_on)) > return 0; > > ? > > Konrad Got it. Will update it next patch.