From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE1292904; Sat, 16 Aug 2025 01:02:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755306178; cv=none; b=Ryh+Bs6Gli4VSKWSvNS5+NBMNE6sdzL3NPwe3/vrtmkMVnJN0u/FtlyabV8xsZEKB1NKmteiCARFHv7U7vocItDO2WlxUNOBFAhKzEl70UhmHVtu78nHumY1Xt7z9212ya13ka9mPZ6KoST8ndUR+G9s7zQxygUrzpqMYhq0rx4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755306178; c=relaxed/simple; bh=bdP6nxC1n1U4Koq+jqMh2c4Dcv9Pe823ljba5HI8hTI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=kVTHDjlCUTjTYrPYwKM7pelLJCBSYB3f5s34x98KWS9xDhjriiKL7tYH4usrFuycxpgFS6iyu1LfZZPXWiFIXpBXWp45dNZc+bhD5dCGW+79xj12Alfl4/qA6hTN0v5/bghoXYypyZWOiV4SZvNO0rbGebQIrSjyWt9q/2ZRsh0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=DtwVebt2; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="DtwVebt2" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=uL1GIBvtGp9qBxNEgGd9zVR3Ww4bteJizXBxx4LVKvs=; b=DtwVebt2cPukDWsmBxLRl1g78u DqhE4zATJgulz++m6XYvVtziVYvIva8IqXNIVL6e6nusqUoAoBwIoj/VEzHq9WN2Rva18nFtm3oTj n3MCpOlxE4z5lVZVRqcm/Y0gGM8bsjyo9Yr5/AbOcelka9ZkhUb1JFNC7PxJywNOKj44=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1un5Jf-004sU0-Qg; Sat, 16 Aug 2025 03:02:39 +0200 Date: Sat, 16 Aug 2025 03:02:39 +0200 From: Andrew Lunn To: Marc Olberding Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] ARM: dts: aspeed: Add device tree for mgx4u BMC Message-ID: <21ee5045-632f-486c-962e-9e2963f60ed4@lunn.ch> References: <20250815-mgx4u_devicetree-v1-0-66db6fa5a7e4@nvidia.com> <20250815-mgx4u_devicetree-v1-3-66db6fa5a7e4@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250815-mgx4u_devicetree-v1-3-66db6fa5a7e4@nvidia.com> > +&mac3 { > + phy-mode = "rgmii"; Does the PCB have extra long clock lines to impose the 2ns delay? Andrew