From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m3293.qiye.163.com (mail-m3293.qiye.163.com [220.197.32.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 861EB153598 for ; Wed, 11 Feb 2026 14:31:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.93 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770820275; cv=none; b=VZqOYBaiHCJzaQQPW+B91qXrrc/u4UyZFJx8TnxOfzemDo/Dv8IpaUjglyfPxO50V0pCDeTVH4kLSAxqw+CQkSLkwD1GkPFP+f8Usp12y0KbJTWbx8xDlW8f7hkmjZZ46osADINzghkpt/Jm2pCdribZxuyaPrgHwBoalHbsro0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770820275; c=relaxed/simple; bh=SeergfIQO6Z9ei9wxKp0oQPyEzoZ/KiS3WLW/GNsvH8=; h=Cc:Subject:To:References:From:Message-ID:Date:MIME-Version: In-Reply-To:Content-Type; b=EXiNoZ1z9FKws6mFV0daYTcv1ZjETlvCQzzOIqn3EzPQaILg91DjjeheWVAAl1DVqsyljAQ5Y9phfjr4SWaCJq3FB1+yNnXtCFfk/UWfFVjw6IEPwlQetCYylHlpEYqfOjiHmPi4930rO/fkJ4xoRdp6e6RIfKYHSGn4bXMf6Bk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=Wc4O1Dxp; arc=none smtp.client-ip=220.197.32.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="Wc4O1Dxp" Received: from [172.16.12.14] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 33e12f8f4; Wed, 11 Feb 2026 22:31:04 +0800 (GMT+08:00) Cc: shawn.lin@rock-chips.com, quentin.schulz@cherry.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: Re: [PATCH v2 4/4] arm64: dts: rockchip: Make Jaguar PCIe-refclk pin use pull-up config To: Heiko Stuebner References: <20260210080303.680403-1-heiko@sntech.de> <20260210080303.680403-5-heiko@sntech.de> From: Shawn Lin Message-ID: <21f56816-e616-f353-c945-dd49cf34b0cf@rock-chips.com> Date: Wed, 11 Feb 2026 22:31:02 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20260210080303.680403-5-heiko@sntech.de> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9c4d1ce25909cckunm430335901141a9 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhgeH1YeGBpIQ0hITBhMS0pWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=Wc4O1Dxp4Am6HwCKvaxUnxCsPZcq7kUgtEBK5kUUS9IKC4eAkZHNw3pePazHGC0zOfw/Ciwy6AIKvjBqHSI5FQTUDlaAZFtIlMJTei4XHQwqBOCeJHFXXIDYD9uy8oTOmimcRT0vWC+/ToBGxHC+tVTI6k7zSjA3dYQAzjqhVsI=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=hxmu4o5Owrd/s+GWT59foXAajtPwkD1n1OFz15Tl5zM=; h=date:mime-version:subject:message-id:from; ÔÚ 2026/02/10 ÐÇÆÚ¶þ 16:03, Heiko Stuebner дµÀ: > From: Heiko Stuebner > > Different to RK3588-Tiger, on RK3588-Jaguar the signal enabling the > PCIe-refclk generator controls a transistor which in turn controls the > output-enable input of the PI6C557 and there's no external Pull-Up or > Pull-Down between the SoC and the transistor gate. > > On Tiger the pin is directly connected to the PDn input which has an > internal pull up. > > So match that behaviour on Jaguar by changing the pin config to enable > the SoC's pull-up config. > > Suggested-by: Quentin Schulz > Fixes: 0ec7e1096332 ("arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar") > Signed-off-by: Heiko Stuebner > --- > arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts > index e21ad7575cb6..5f5d89a33a4a 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts > @@ -579,7 +579,7 @@ led1_pin: led1-pin { > > pcie30x4 { > pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 { > - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; > + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; If Jaguar need support L1 substate, I guess it should be changed to fucntion IO again instead of GPIO. From the refclk design which uses pcie30x4_clkreqn_m0 as enable control in active low mode , it's fine to support these low power mode. Otherwise, fine with me Reviewed-by: Shawn Lin > }; > > pcie30x4_perstn_m0: pcie30x4-perstn-m0 { >