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Sat, 15 Nov 2025 05:53:47 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5AF5rkUN010797 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 15 Nov 2025 05:53:46 GMT Received: from [10.216.38.157] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 14 Nov 2025 21:53:39 -0800 Message-ID: <22350774-20da-42ff-a6c2-02fab121f4b5@quicinc.com> Date: Sat, 15 Nov 2025 11:23:30 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/3] arm64: dts: qcom: monaco-evk-camera: Add DT overlay To: Konrad Dybcio , Vikram Sharma , , , , , , , , , , , CC: , , , , , , Ravi Shankar , Vishal Verma , Vladimir Zapolskiy References: <20251114064541.446276-1-quic_vikramsa@quicinc.com> <20251114064541.446276-4-quic_vikramsa@quicinc.com> Content-Language: en-US From: Nihal Kumar Gupta In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE1MDA0NiBTYWx0ZWRfX5OxJQXPM193g stAn1JeRwBliK55fXewzsEyJGSawrtugqFizZuDvIszIkCaQdcd8AJuww38dMMktAi2i1xfOLoi XjzytoMPSaVpUy4Eq9CIzhJLMjoTFqdHhQD9dC/TUnk0ojNusnhwYuhbGqv7bejCYz8vvBf+/e4 vVPiU1aeSq5simOtjWpXW1Xf22BopsofaZcEgwWXA+8MHEd+v6GGU+2CFlM19cRXDyiFB3J6in8 Waf9XkPIptBLQI5VByYTjp5mCSeLXcKYm8vDKFByuhvwV8ffrjz8QQSdigtThAbvl2odRh4ePoG ahgx7IXgKst+m8fq0NJ6QHrEBkj5YYj92zCf+7ZdRtBVAxTENTnR5ESZN7wo+Vp6E08SGIzTE3I vd69MkFEcs34Y9n9rHMwAa5shtAfEA== X-Proofpoint-GUID: tHKamVMcx8f6uAcjWA9C5Cik_mG7iFvA X-Authority-Analysis: v=2.4 cv=E4vAZKdl c=1 sm=1 tr=0 ts=6918156b cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=mZF60CUetaME7T47FmQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-ORIG-GUID: tHKamVMcx8f6uAcjWA9C5Cik_mG7iFvA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-15_02,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 suspectscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511150046 On 15-11-2025 03:49, Konrad Dybcio wrote: >> +&{/} { >> + vreg_cam1_2p8: vreg-cam1-2p8 { > Where does this regulator lie physically? Is its presence dependent > on the connection of the sensor, is it part of the EVK carrier board, > or perhaps something else? vreg_cam1_2p8 is a fixed 2.8 V regulator located on the EVK carrier board. It supplies the camera sensor’s AVDD rail and is enabled via GPIO 74, which is controlled by the TLMM block. > >> + compatible = "regulator-fixed"; >> + regulator-name = "vreg_cam1_2p8"; >> + startup-delay-us = <10000>; >> + enable-active-high; >> + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&cam1_avdd_2v8_en_default>; > property-n > property-names > > please > ACK > [...] > >> +&tlmm { >> + /* >> + * gpio67, gpio68, gpio69 provide MCLK0, MCLK1, MCLK2 for >> + * CAM0, CAM1 and CAM2 respectively via the "cam_mclk" function. >> + * So, here it's MCLK1 pin for instance. >> + */ > I don't really see the value in these comments.. > > Vladimir requested you to move the 'description' (meaning the node > describing the hardware, not a comment explaining the function of the > DT hunk in natural language) to monaco.dtsi too I’ve added descriptions to indicate which pins enable which camera MCLK/Regulators. If these aren’t considered useful, I can remove them. Should I need to add hardware descriptions for all GPIOs (gpio67–69 for MCLK and gpio73–75 for regulator enable), even if they are unused? I have referenced qcs6490-rb3gen2-vision-mezzanine.dtso for the MCLK pin hardware description (cam1_default). All TLMM GPIOs mentioned above are muxed pins. As Bryan suggested in v4, these should go into the mezzanine-specific dtso. Do I need to extend this in monaco.dtsi as well? -- Regards, Nihal Kumar Gupta