From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7B3CC433FE for ; Fri, 18 Nov 2022 18:11:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242506AbiKRSLl (ORCPT ); Fri, 18 Nov 2022 13:11:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234994AbiKRSLi (ORCPT ); Fri, 18 Nov 2022 13:11:38 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5BEF8754C; Fri, 18 Nov 2022 10:11:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668795097; x=1700331097; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=qySCtFgqmMLMr3vc7i29wNNm4ljo0VreS/eNDPEYfm0=; b=dqw73ia+dtN8h8MAV0o/v8zJ/LyVsVmV9PIxPnGqDNkchUiNdbtOqzfB 8/1QO0/Ayg/9ln3TKxRMUbB0nxIUzOdnx5R9T84OFkHwvpmWc+1HJmqIc cV2UA/KA8PD0DWTH/zTNnFQbo+0/ADEoMaysJYN59d+MlTX6SVgsPSK59 PkO0LtNQdO5bRZXSYY8+W/vkbwq1t9TQx14urixBK0KDUihugnO7gerpu 5yYTkxgBnSBgpVGf6TAlxOQmZEV9gjO6ZdQzkwxDNbP5iuVlI/8AVEPEx vHw56Yl7qmZTL3M/mkyVK7fDNJt/ktBu2Z4Kkihcy89l8V9dqcEPbKZmm g==; X-IronPort-AV: E=McAfee;i="6500,9779,10535"; a="399485818" X-IronPort-AV: E=Sophos;i="5.96,175,1665471600"; d="scan'208";a="399485818" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 10:11:37 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10535"; a="969361767" X-IronPort-AV: E=Sophos;i="5.96,175,1665471600"; d="scan'208";a="969361767" Received: from mbeebe-mobl1.amr.corp.intel.com (HELO [10.209.82.240]) ([10.209.82.240]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 10:11:36 -0800 Message-ID: <22398efc-15c2-4cc5-87a1-7c47c762b283@intel.com> Date: Fri, 18 Nov 2022 10:11:35 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v3 1/2] x86/tsx: Add feature bit for TSX control MSR support Content-Language: en-US To: Pawan Gupta , Andrew Cooper , thomas.lendacky@amd.com, "H. Peter Anvin" , hdegoede@redhat.com, Ingo Molnar , "Rafael J. Wysocki" , Thomas Gleixner , x86@kernel.org, Pavel Machek , Dave Hansen , David.Kaplan@amd.com, Borislav Petkov Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Daniel Sneddon , antonio.gomez.iglesias@linux.intel.com References: From: Dave Hansen In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/15/22 11:17, Pawan Gupta wrote: > Support for TSX control MSR is enumerated in MSR_IA32_ARCH_CAPABILITIES. > This is different from how other CPU features are enumerated i.e. via > CPUID. Currently a call to tsx_ctrl_is_supported() is required for > enumerating the feature. In the absence of feature bit for TSX control, > any code that relies on checking feature bits directly will not work. > > In preparation for adding a feature bit check in MSR save/restore during > suspend/resume, set a new feature bit X86_FEATURE_TSX_CTRL when > MSR_IA32_TSX_CTRL is present. Also make tsx_ctrl_is_supported() use the > new feature bit to avoid any overhead of reading the MSR. Reviewed-by: Dave Hansen