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[89.162.31.138]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm318964lfr.40.2022.07.21.02.04.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jul 2022 02:04:03 -0700 (PDT) Message-ID: <226ac31e-2ac4-cb73-ab67-62f86d5e5783@linaro.org> Date: Thu, 21 Jul 2022 11:04:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v4 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Content-Language: en-US To: wangseok.lee@samsung.com, "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" Cc: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim References: <20220720055108epcms2p563c65b3de6333ccbc68386aa2471a800@epcms2p5> <20220720060112epcms2p30a05414992cf814e5886af2b70c0f58f@epcms2p3> From: Krzysztof Kozlowski In-Reply-To: <20220720060112epcms2p30a05414992cf814e5886af2b70c0f58f@epcms2p3> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/07/2022 08:01, Wangseok Lee wrote: > Add support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis > Communications. This is based on arm64 and support GEN4 & 2lane. This > PCIe controller is based on DesignWare Hardware core and uses DesignWare > core functions to implement the driver. "pcie-artpec6. c" supports artpec6 > and artpec7 H/W. artpec8 can not be expanded because H/W configuration is > completely different from artpec6/7. PHY and sub controller are different. > > Signed-off-by: Wangseok Lee > Signed-off-by: Jaeho Cho > --- > v3->v4 : > -Remove unnecessary enum type > -Fix indentation > Thanks for the changes. This starts to look good, however I am not going to ack it. This is also not a strong NAK, as I would respect Bjorn and other maintainers decision. I don't like the approach of creating only Artpec-8 specific driver. Samsung heavily reuses its block in all Exynos devices. Now it re-uses them for other designs as well. Therefore, even if merging with existing Exynos PCIe driver is not feasible (we had such discussions), I expect this to cover all Samsung Foundry PCIe devices. From all current designs up to future licensed blocks, including some new Samsung Exynos SoC. Or at least be ready for it. However it seems you are interested only in achieving one goal here - satisfy Axis. I believe it is not the "upstream approach". Next month you come up with same driver for different customer and you keep insisting "it's different!". To get my ack I want to see something generic for Samsung Exynos SoC and other licensed or designed blocks, instead of something made for only one of your customers. Best regards, Krzysztof