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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDAzMCBTYWx0ZWRfX5vayVlaPRT6j aoz510zY9Usqv979rcxAT84k8VI+A8KGFnJup4dZA85gU6gDm16SlhvjO0rHd5e1stRwJGvNdRJ edRQAoHCSfNQ9J3uAJ/RvL0O/w8jaWI= X-Proofpoint-GUID: DA_RgduhUjknAhaHJzy6ESlGOAz1TUzj X-Authority-Analysis: v=2.4 cv=NddzRGD4 c=1 sm=1 tr=0 ts=6acc8de8 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=mFIT96Bc5s7vh8gnFTIA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDAzMCBTYWx0ZWRfX4PKxSZrjzFhz 85tvY8tw367b4cJUAwqqBZat+XpEvgr+9OSzh8GdE14W2fMOijBab1o4Sv8Y72KWoQf7lVbRKnG bFsoLpy2vutQsScNxqYg4p9dcothGgbdny3C1t01OVtPaFHsZ9jEEabepCxYzeZYwXc4Ux5fp50 f64lwyKpLw0krq7qzFQTL0YlR47+QZPuDVxekkEwTYvMdXPhyii6+3w6zxhbFkEZyqUe7ctynSp 4sr5IzVl8JWC4i77gNZfCjtidQYLeoNyEwrvMUvRuQJKc6+3egpngL5joGlAKZAyEOs6dApmj1I replNRtNR/OmTTobXaID8NXvVTmAaiaoe4TP7AR0jUD7vcLrQPDaAKYZFEkL9cTl1khwjSUaYfJ D38U7df+ov/C+n8x+QflHjyrPmqqRK0vcXGqzdHNX30M0mRmlJl1TCkAWPYvKoHqAQ+4IVxLeVI 9HfSMTuW4LTm4oN8seQ== X-Proofpoint-ORIG-GUID: DA_RgduhUjknAhaHJzy6ESlGOAz1TUzj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_02,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 impostorscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 suspectscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610120030 On 10/9/26 2:55 PM, Krishna Chaitanya Chundru wrote: > The PARF write, read and BDF halt features make the controller wait > for earlier AXI transactions to complete before issuing new ones. This > is needed on SoCs whose NoC cannot preserve the ordering of inbound > transactions from the controller. > > On newer SoCs, the NoC preserves this ordering on its own. Halting at > the controller adds no correctness benefit and reduces inbound DMA > bandwidth. Please explain what makes a SoC go into the "newer" category in this context Konrad