From: Stefan Bruens <stefan.bruens@rwth-aachen.de>
To: "André Przywara" <andre.przywara@arm.com>
Cc: <linux-sunxi@googlegroups.com>, <devicetree@vger.kernel.org>,
<dmaengine@vger.kernel.org>, Vinod Koul <vinod.koul@intel.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,
Code Kipper <codekipper@gmail.com>
Subject: Re: [PATCH 07/10] dmaengine: sun6i: Retrieve channel count/max request from devicetree
Date: Mon, 4 Sep 2017 02:12:07 +0200 [thread overview]
Message-ID: <2286861.ip18xhFNEq@pebbles.site> (raw)
In-Reply-To: <d211b11c-09f6-8a69-2560-6be89f3b9c3c@arm.com>
On Montag, 4. September 2017 01:44:54 CEST André Przywara wrote:
> Hi,
>
> On 03/09/17 23:40, Stefan Brüns wrote:
> > To avoid introduction of a new compatible for each small SoC/DMA
> > controller
> > variation, move the definition of the channel count to the devicetree.
> >
> > The number of vchans is no longer explicit, but limited by the highest
> > port/DMA request number. The result is a slight overallocation for SoCs
> > with a sparse port mapping.
> >
> > Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
> > ---
> >
> > drivers/dma/sun6i-dma.c | 35 ++++++++++++++++++++++++++++++++++-
> > 1 file changed, 34 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> > index c69dadb853d2..bd4c2e4a759b 100644
> > --- a/drivers/dma/sun6i-dma.c
> > +++ b/drivers/dma/sun6i-dma.c
> > @@ -42,6 +42,9 @@
> >
> > #define DMA_STAT 0x30
> >
> > +/* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels
> > */
> > +#define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4)
> > +
> >
> > /*
> >
> > * sun8i specific registers
> > */
> >
> > @@ -65,7 +68,8 @@
> >
> > #define DMA_CHAN_LLI_ADDR 0x08
> >
> > #define DMA_CHAN_CUR_CFG 0x0c
> >
> > -#define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f)
> > +#define DMA_CHAN_MAX_DRQ 0x1f
> > +#define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & DMA_CHAN_MAX_DRQ)
> >
> > #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5)
> > #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5)
> > #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7)
> >
> > @@ -1173,6 +1177,35 @@ static int sun6i_dma_probe(struct platform_device
> > *pdev)>
> > sdc->num_vchans = sdc->cfg->nr_max_vchans;
> > sdc->max_request = sdc->cfg->nr_max_requests;
> >
> > + ret = of_property_read_u32(np, "dma-channels", &sdc->num_pchans);
> > + if (ret && !sdc->num_pchans) {
> > + dev_err(&pdev->dev, "Can't get dma-channels.\n");
> > + return ret;
> > + }
> > +
> > + if (sdc->num_pchans > DMA_MAX_CHANNELS) {
> > + dev_err(&pdev->dev, "Number of dma-channels out of range.\n");
> > + return -EINVAL;
> > + }
> > +
> > + ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
> > + if (ret && !sdc->max_request) {
> > + dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
> > + DMA_CHAN_MAX_DRQ);
>
> Mmmh, is this mapping of "!sdc->max_request" -> DMA_CHAN_MAX_DRQ
> implemented somewhere else? Or is it just missing here:
> sdc->max_request = DMA_CHAN_MAX_DRQ;
Well spotted, that assignment is actually missing.
With this line added, your comment for patch 8/10 should also be addressed
(regarding the default value).
> Otherwise this is looking good, thanks for picking up the DT property
> approach!
>
> Cheers,
> Andre.
>
Kind regards,
Stefan
--
Stefan Brüns / Bergstraße 21 / 52062 Aachen
home: +49 241 53809034 mobile: +49 151 50412019
next prev parent reply other threads:[~2017-09-04 0:12 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-03 22:40 [PATCH 00/10] dmaengine: sun6i: Fixes for H3/A83T, enable A64 Stefan Brüns
2017-09-03 22:40 ` [PATCH 01/10] dmaengine: sun6i: Correct setting of clock autogating register for A83T/H3 Stefan Brüns
2017-09-03 23:23 ` André Przywara
2017-09-04 7:06 ` Maxime Ripard
2017-09-03 22:40 ` [PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 Stefan Brüns
2017-09-04 7:59 ` Maxime Ripard
2017-09-04 14:47 ` Brüns, Stefan
2017-09-03 22:40 ` [PATCH 03/10] dmaengine: sun6i: Restructure code to allow extension for new SoCs Stefan Brüns
2017-09-03 22:40 ` [PATCH 04/10] dmaengine: sun6i: Enable additional burst lengths/widths on H3 Stefan Brüns
2017-09-04 8:00 ` Maxime Ripard
2017-09-03 22:40 ` [PATCH 05/10] dmaengine: sun6i: Move number of pchans/vchans/request to device struct Stefan Brüns
2017-09-04 7:43 ` Maxime Ripard
2017-09-04 14:30 ` Brüns, Stefan
2017-09-08 14:37 ` Maxime Ripard
2017-09-03 22:40 ` [PATCH 06/10] arm64: allwinner: a64: Add devicetree binding for DMA controller Stefan Brüns
2017-09-12 16:52 ` Rob Herring
2017-09-03 22:40 ` [PATCH 07/10] dmaengine: sun6i: Retrieve channel count/max request from devicetree Stefan Brüns
2017-09-03 23:44 ` André Przywara
2017-09-04 0:12 ` Stefan Bruens [this message]
2017-09-03 22:40 ` [PATCH 08/10] dmaengine: sun6i: Add support for Allwinner A64 and compatibles Stefan Brüns
2017-09-03 23:37 ` André Przywara
2017-09-04 0:13 ` Stefan Bruens
2017-09-03 22:41 ` [PATCH 09/10] arm64: allwinner: a64: Add device node for DMA controller Stefan Brüns
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