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header.from=amd.com; Received: from DM4PR12MB5070.namprd12.prod.outlook.com (2603:10b6:5:389::22) by DM4PR12MB8449.namprd12.prod.outlook.com (2603:10b6:8:17f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8922.32; Wed, 16 Jul 2025 13:09:53 +0000 Received: from DM4PR12MB5070.namprd12.prod.outlook.com ([fe80::20a9:919e:fd6b:5a6e]) by DM4PR12MB5070.namprd12.prod.outlook.com ([fe80::20a9:919e:fd6b:5a6e%7]) with mapi id 15.20.8922.035; Wed, 16 Jul 2025 13:09:52 +0000 Message-ID: <229325e8-a461-6e5c-0d32-1c36086b62f7@amd.com> Date: Wed, 16 Jul 2025 08:09:48 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 To: Nikunj A Dadhania , linux-kernel@vger.kernel.org, bp@alien8.de, x86@kernel.org Cc: seanjc@google.com, tglx@linutronix.de, mingo@redhat.com, dave.hansen@linux.intel.com, santosh.shukla@amd.com References: <20250716055315.2229037-1-nikunj@amd.com> Content-Language: en-US From: Tom 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On 7/16/25 00:53, Nikunj A Dadhania wrote: > From: Sean Christopherson > > Currently, when a Secure TSC enabled SNP guest attempts to write to the > intercepted GUEST_TSC_FREQ MSR (a read-only MSR), the guest kernel response > incorrectly implies a VMM configuration error, when in fact it is the usual > VMM configuration to intercept writes to read-only MSRs, unless explicitly > documented. > > Modify the intercepted TSC MSR #VC handling: > * Write to GUEST_TSC_FREQ will generate a #GP instead of terminating the > guest > * Write to MSR_IA32_TSC will generate a #GP instead of silently ignoring it > > Add a WARN_ONCE to log the incident, as well-behaved SNP guest kernels > should never attempt to write to these MSRs. > > However, continue to terminate the guest when reading from intercepted > GUEST_TSC_FREQ MSR with Secure TSC enabled, as intercepted reads indicate > an improper VMM configuration for Secure TSC enabled SNP guests. > > Signed-off-by: Sean Christopherson > Co-developed-by: Nikunj A Dadhania > Signed-off-by: Nikunj A Dadhania > --- > arch/x86/coco/sev/vc-handle.c | 31 ++++++++++++++++--------------- > 1 file changed, 16 insertions(+), 15 deletions(-) > > diff --git a/arch/x86/coco/sev/vc-handle.c b/arch/x86/coco/sev/vc-handle.c > index faf1fce89ed4..18be9f8bd015 100644 > --- a/arch/x86/coco/sev/vc-handle.c > +++ b/arch/x86/coco/sev/vc-handle.c > @@ -371,29 +371,30 @@ static enum es_result __vc_handle_msr_caa(struct pt_regs *regs, bool write) > * executing with Secure TSC enabled, so special handling is required for > * accesses of MSR_IA32_TSC and MSR_AMD64_GUEST_TSC_FREQ. > */ > -static enum es_result __vc_handle_secure_tsc_msrs(struct pt_regs *regs, bool write) > +static enum es_result __vc_handle_secure_tsc_msrs(struct pt_regs *regs, bool write, > + struct es_em_ctxt *ctxt) The pt_regs pointer is part of the es_em_ctxt struct, so probably just change this to: static enum es_result __vc_handle_secure_tsc_msrs(struct es_em_ctxt *ctxt, bool write) and then get the regs pointer from ctxt: struct pt_regs *regs = ctxt->regs; > { > u64 tsc; > > /* > - * GUEST_TSC_FREQ should not be intercepted when Secure TSC is enabled. > - * Terminate the SNP guest when the interception is enabled. > + * Writing to MSR_IA32_TSC can cause subsequent reads of the TSC to > + * return undefined values, and GUEST_TSC_FREQ is read-only. Generate > + * a #GP on all writes, but WARN to log a kernel bug. > */ > - if (regs->cx == MSR_AMD64_GUEST_TSC_FREQ) > - return ES_VMM_ERROR; > + if (WARN_ON_ONCE(write)) { Do we want to capture individual WARNs for each MSR? I guess I'm ok with a single WARN for either MSR, but just asking the question. Thanks, Tom > + ctxt->fi.vector = X86_TRAP_GP; > + ctxt->fi.error_code = 0; > + return ES_EXCEPTION; > + } > > /* > - * Writes: Writing to MSR_IA32_TSC can cause subsequent reads of the TSC > - * to return undefined values, so ignore all writes. > - * > - * Reads: Reads of MSR_IA32_TSC should return the current TSC value, use > - * the value returned by rdtsc_ordered(). > + * GUEST_TSC_FREQ read should not be intercepted when Secure TSC is > + * enabled. Terminate the SNP guest when the interception is enabled. > */ > - if (write) { > - WARN_ONCE(1, "TSC MSR writes are verboten!\n"); > - return ES_OK; > - } > + if (regs->cx == MSR_AMD64_GUEST_TSC_FREQ) > + return ES_VMM_ERROR; > > + /* Reads of MSR_IA32_TSC should return the current TSC value. */ > tsc = rdtsc_ordered(); > regs->ax = lower_32_bits(tsc); > regs->dx = upper_32_bits(tsc); > @@ -416,7 +417,7 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) > case MSR_IA32_TSC: > case MSR_AMD64_GUEST_TSC_FREQ: > if (sev_status & MSR_AMD64_SNP_SECURE_TSC) > - return __vc_handle_secure_tsc_msrs(regs, write); > + return __vc_handle_secure_tsc_msrs(regs, write, ctxt); > break; > default: > break; > > base-commit: 9f4a425223f3bd8ccaebc7f4f42b1d8c5f12fb45