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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ba451210e26sm772516066b.8.2026.04.24.03.58.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Apr 2026 03:58:59 -0700 (PDT) Message-ID: <22b97f4d-ea71-4838-98cc-470dbca728c6@oss.qualcomm.com> Date: Fri, 24 Apr 2026 12:58:56 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/5] phy: qcom: qmp-pcie: Add PCIe Gen5 8-lane bifurcation support for Glymur To: Neil Armstrong , Qiang Yu Cc: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260304-glymur_gen5x8_phy-v1-0-849e9a72e125@oss.qualcomm.com> <42a9dd4d-eb96-42c0-b836-dcd7cb9405ff@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: wLejM5hpmbPjzuQwTbs_MEpwFBUgH4XK X-Authority-Analysis: v=2.4 cv=QLhYgALL c=1 sm=1 tr=0 ts=69eb4cf5 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=Btiq9F5UgLBRDrkW77oA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-GUID: wLejM5hpmbPjzuQwTbs_MEpwFBUgH4XK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI0MDEwMyBTYWx0ZWRfX9V7JP9//MyVS z9eXcEs9uod3FNciKe93dgjHBt3PWF6aGj343rX8z1xgxugfCGTkQLuCT3NUp51Adn0z0+GWNLz 3qUB/N/Bu/gz3W/HhZek2KUEjVVpcFTSaki012JGDsf6lJltYt9F0EwasQjEZKKoM18k6yLnLNv ZUG5B7g5HE9C6piNWO4PYYp+qxyVrHE6neeeZe6UIDzQTELhN9gJiVzsVHuECLqBW/w8Ipn6fKX /+9PlIPLjzLLI3DlDOFbO8+xzN3bB1DdgEpkVfygDYkvld1VGt0ZwTUls+gm9EkYLvaeU2sIVZi YTbwtjbLRWt6B62IsxSTf6bejIAivg/or2+xel+KznWjifu5bp5HTCPN3nULU/8Kcg+z6Ikz1bL HAzIyHurjpkiGjy/QMBH3DIB0ZinmV8F3GTNop06LKqZYy3xS7kZYW/2gM5RaITMPxIHdw4rUpk AKm9Jlzz4RVUla41SWA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604240103 On 3/6/26 11:34 AM, Neil Armstrong wrote: > On 3/6/26 10:26, Qiang Yu wrote: >> On Thu, Mar 05, 2026 at 10:14:05AM +0100, Konrad Dybcio wrote: >>> On 3/4/26 9:21 AM, Qiang Yu wrote: >>>> This patch series adds support for PCIe Gen5 8-lane bifurcation mode on >>>> the Glymur SoC's third PCIe controller. In this configuration, pcie3a PHY >>>> acts as leader and pcie3b PHY as follower to form a single 8-lane PCIe >>>> Gen5 interface. >>>> >>>> To support 8-lanes mode, this patch series add multiple power domain and >>>> multi nocsr reset infrastructure as the hardware programming guide >>>> specifies a strict initialization sequence for bifurcation mode that >>>> requires coordinated multi-PHY resource management: >>>> >>>> 1. Turn on both pcie3a_phy_gdsc and pcie3b_phy_gdsc power domains >>>> 2. Assert both pcie3a and pcie3b nocsr resets, then deassert them together >>>> 3. Enable all pcie3a PHY clocks and pcie3b PHY aux clock (bifur_aux) >>>> 4. Poll for PHY ready status >>> >>> I think we never concluded the discussion where I suggested the >>> bifurcated PHY may be better expressed as a single node with >>> #phy-cells = <1>, removing the need for duplicated resource references > > DT requires strict hardware description, no abstraction for HW, so if there's > 2 PHYs, then add 2 separate phys and reference them from the PCie controller. A single device *is* the strict HW description here. There's a single shared top-level set of controls (mostly in the "COM[mon]" block) and 8 PCIe lanes that are (roughly speaking) unaware of what configuration they're in This is very much analogous to the USB3+DP combo PHY, where the USB and DP parts are reasonably separate (you can turn the USB or the DP part off independently), but those are building blocks that are sort of just two "front-ends" to the rest of the QMPPHY hardware, that process data from the otherwise unaware pairs of lanes in one configuration or another Konrad