From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C6E22C11D9 for ; Thu, 4 Dec 2025 12:12:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764850344; cv=none; b=ZVdBN3C/la4xCmE0TtDVGlDSXi1oMfMRp4N+kDPZQtLNJW3DKjkbbANKXTlP7jEwO6g7E5yeoXEx/8BLH2VD4MQkKGeFRBed7JanCo/Xc/8KwfZq9t8r4sbbZUhdbcd1c2Ncj5Yid+xXT8L5WNaKT+lIQfzh1DZym/UX4FKl7qo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764850344; c=relaxed/simple; bh=MuqajGwfhj3xCGfoQBWQRUMFLnPMA7ZJP0BEJMHlEgs=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=TaFzjP35LNLxiJyQ0FFU+1xheL2A1txqyTMbqq5yqlodk/6AYu43VJbyavyv2Edma4iX993T9CfES0XobW00ioQrf52D9u2LtilNA81sO9omx7Ajx/uq806Hba4NCxDigN9FJ32KKKHldSTYY0yxcOvqC0b7KwsiMOM4mM/iXBY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mFHyZRom; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mFHyZRom" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764850342; x=1796386342; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=MuqajGwfhj3xCGfoQBWQRUMFLnPMA7ZJP0BEJMHlEgs=; b=mFHyZRoms4z+hhRJ9eRMa9rUhVrO9NX3annS981lmoRBBkfYAY4BMvVM aEYWi7wjscqUDiR/XT2QUpckeOLy4bovTAwfzmNGsQ8wq9UHbhINVYIQy OKUIfl/D2k0c4azT0tHsyBtveWnFDT9/kv3liv7qt/LsJF42O7sadgQed mJjvQ+IZq0b+Ibb0q5EWEcsVPmuZfa9kcKwU8zlxfSOB66woapxZRDHL6 Zpg5SuluTkCJVjpYhifDpVIDZybCLJRcoaCLvjvaClVfPgitM5v+tYtgs VdVVvB7dXU31rMsScRnqLbppYAdzLCBwUliAKSkr2GkQny2z2yJLtPDm8 A==; X-CSE-ConnectionGUID: 5AAewNfwR3+U+FhMKdBq1A== X-CSE-MsgGUID: +9dZ6vquSQuQwAwWrG+Vtg== X-IronPort-AV: E=McAfee;i="6800,10657,11631"; a="77547484" X-IronPort-AV: E=Sophos;i="6.20,248,1758610800"; d="scan'208";a="77547484" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2025 04:12:22 -0800 X-CSE-ConnectionGUID: mah35uXRTZuwN87oCwh9mw== X-CSE-MsgGUID: AvrZViaOTk+vFXc36Jwmsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,248,1758610800"; d="scan'208";a="200097039" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.11]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2025 04:12:16 -0800 From: Jani Nikula To: Yaroslav Bolyukin , Ville =?utf-8?B?U3lyasOkbMOk?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , Christian =?utf-8?Q?K=C3=B6nig?= , Wayne Lin , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yaroslav Bolyukin Subject: Re: [PATCH v7 6/7] drm/edid: parse DRM VESA dsc bpp target In-Reply-To: <20251202110218.9212-7-iam@lach.pw> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251202110218.9212-1-iam@lach.pw> <20251202110218.9212-7-iam@lach.pw> Date: Thu, 04 Dec 2025 14:12:12 +0200 Message-ID: <22d49b0cd8b52f485c51af530f49cd8771b2634c@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, 02 Dec 2025, Yaroslav Bolyukin wrote: > As per DisplayID v2.1a spec "DSC pass-through timing support", > VESA vendor-specific data block may contain target DSC bits per pixel > fields, that should be always used for the VII modes that declare they > only support working with this value (Pass-through Timing Support for > Target DSC Bits per Pixel). > > Signed-off-by: Yaroslav Bolyukin > > fixup parse DRM vesa dsc bpp target Needs to be removed while applying, no need to resend for this. Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/drm_displayid_internal.h | 4 ++++ > drivers/gpu/drm/drm_edid.c | 17 +++++++++++++++++ > include/drm/drm_connector.h | 6 ++++++ > 3 files changed, 27 insertions(+) > > diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h > index 55f972d32847..8f1a2f33ca1a 100644 > --- a/drivers/gpu/drm/drm_displayid_internal.h > +++ b/drivers/gpu/drm/drm_displayid_internal.h > @@ -148,6 +148,8 @@ struct displayid_formula_timing_block { > #define DISPLAYID_VESA_DP_TYPE GENMASK(2, 0) > #define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0) > #define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5) > +#define DISPLAYID_VESA_DSC_BPP_INT GENMASK(5, 0) > +#define DISPLAYID_VESA_DSC_BPP_FRACT GENMASK(3, 0) > > #define DISPLAYID_VESA_DP_TYPE_EDP 0 > #define DISPLAYID_VESA_DP_TYPE_DP 1 > @@ -157,6 +159,8 @@ struct displayid_vesa_vendor_specific_block { > u8 oui[3]; > u8 data_structure_type; > u8 mso; > + u8 dsc_bpp_int; > + u8 dsc_bpp_fract; > } __packed; > > /* > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index be8715632b91..8273920f5ba4 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -45,6 +45,7 @@ > #include > #include > #include > +#include > #include > > #include "drm_crtc_internal.h" > @@ -6593,6 +6594,21 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector, > } else { > info->mso_pixel_overlap = 0; > } > + > + if (block->num_bytes < 7) { > + /* DSC bpp is optional */ > + return; > + } > + > + info->dp_dsc_bpp_x16 = FIELD_GET(DISPLAYID_VESA_DSC_BPP_INT, vesa->dsc_bpp_int) << 4 | > + FIELD_GET(DISPLAYID_VESA_DSC_BPP_FRACT, vesa->dsc_bpp_fract); > + > + if (info->dp_dsc_bpp_x16 > 0) { > + drm_dbg_kms(connector->dev, > + "[CONNECTOR:%d:%s] DSC bits per pixel " FXP_Q4_FMT "\n", > + connector->base.id, connector->name, > + FXP_Q4_ARGS(info->dp_dsc_bpp_x16)); > + } > } > > static void drm_update_vesa_specific_block(struct drm_connector *connector, > @@ -6641,6 +6657,7 @@ static void drm_reset_display_info(struct drm_connector *connector) > info->mso_stream_count = 0; > info->mso_pixel_overlap = 0; > info->max_dsc_bpp = 0; > + info->dp_dsc_bpp_x16 = 0; > > kfree(info->vics); > info->vics = NULL; > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h > index 8f34f4b8183d..7decfc288aa3 100644 > --- a/include/drm/drm_connector.h > +++ b/include/drm/drm_connector.h > @@ -837,6 +837,12 @@ struct drm_display_info { > */ > u32 max_dsc_bpp; > > + /** > + * @dp_dsc_bpp: DP Display-Stream-Compression (DSC) timing's target > + * DSC bits per pixel in 6.4 fixed point format. 0 means undefined. > + */ > + u16 dp_dsc_bpp_x16; > + > /** > * @vics: Array of vics_len VICs. Internal to EDID parsing. > */ -- Jani Nikula, Intel