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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d149a49dc6sm11352497a12.31.2024.12.13.04.39.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Dec 2024 04:39:52 -0800 (PST) Message-ID: <230eb99b-b223-4d5f-92f6-27edc6827cb0@oss.qualcomm.com> Date: Fri, 13 Dec 2024 13:39:50 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/7] drm/msm: adreno: enable GMU bandwidth for A740 and A750 To: neil.armstrong@linaro.org, Konrad Dybcio , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> <20241211-topic-sm8x50-gpu-bw-vote-v5-5-6112f9f785ec@linaro.org> <31264e68-2cdc-41b2-8d84-459dc257f0f5@oss.qualcomm.com> <76592f0b-85f4-4c84-b45b-859d55c4e87d@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <76592f0b-85f4-4c84-b45b-859d55c4e87d@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: _J4CqiOqCZCxEaltgcURxev3U1XBUxuW X-Proofpoint-ORIG-GUID: _J4CqiOqCZCxEaltgcURxev3U1XBUxuW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 phishscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130089 On 12.12.2024 10:36 PM, Neil Armstrong wrote: > On 12/12/2024 21:32, Konrad Dybcio wrote: >> On 11.12.2024 9:29 AM, Neil Armstrong wrote: >>> Now all the DDR bandwidth voting via the GPU Management Unit (GMU) >>> is in place, declare the Bus Control Modules (BCMs) and the >>> corresponding parameters in the GPU info struct. >>> >>> Reviewed-by: Dmitry Baryshkov >>> Reviewed-by: Akhil P Oommen >>> Signed-off-by: Neil Armstrong >>> --- >>>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 22 ++++++++++++++++++++++ >>>   1 file changed, 22 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..edffb7737a97b268bb2986d557969e651988a344 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> @@ -1388,6 +1388,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>               .pwrup_reglist = &a7xx_pwrup_reglist, >>>               .gmu_chipid = 0x7020100, >>>               .gmu_cgc_mode = 0x00020202, >>> +            .bcms = (const struct a6xx_bcm[]) { >>> +                { .name = "SH0", .buswidth = 16 }, >> >> All a7xx targets use the same BCMs with the only difference being >> the ACV voting mask. You may want to make these non-anonymous structs. > > it can be done in a second step > >> >>> +                { .name = "MC0", .buswidth = 4 }, >>> +                { >>> +                    .name = "ACV", >>> +                    .fixed = true, >>> +                    .perfmode = BIT(3), >>> +                    .perfmode_bw = 16500000, >> >> I think perfmode is simply supposed to be set when bw == max_bw > > Not for a750 Akhil, is there any way to determine a suitable OPP for this dynamically? Konrad