From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756446AbcGGLSc (ORCPT ); Thu, 7 Jul 2016 07:18:32 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:60256 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752013AbcGGLSa (ORCPT ); Thu, 7 Jul 2016 07:18:30 -0400 X-AuditID: cbfee61b-f798b6d00000114d-c8-577e3a83cdf9 From: Bartlomiej Zolnierkiewicz To: Abhilash Kesavan Cc: Sylwester Nawrocki , tomasz.figa@gmail.com, kgene.kim@samsung.com, k.kozlowski@samsung.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/2] clk: samsung: cpu: Prepare for addition for Exynos7 CPU clocks Date: Thu, 07 Jul 2016 13:17:40 +0200 Message-id: <2318982.ZLuIVQzhgE@amdc1976> User-Agent: KMail/4.13.3 (Linux/3.13.0-79-generic; KDE/4.13.3; x86_64; ; ) In-reply-to: <577E32E5.4010902@samsung.com> References: <1467750561-13957-1-git-send-email-a.kesavan@samsung.com> <1467750561-13957-2-git-send-email-a.kesavan@samsung.com> <577E32E5.4010902@samsung.com> MIME-version: 1.0 Content-transfer-encoding: 7Bit Content-type: text/plain; charset=us-ascii X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsVy+t9jAd1mq7pwg51bpC0er1nMZPH6haFF 74KrbBabHl9jtfjYc4/V4vKuOWwWM87vY7K4eMrV4vCbdlaLH2e6WSxW7frD6MDt8f5GK7vH 5b5eJo+ds+6ye2xeUu/Rt2UVo8fnTXIBbFFcNimpOZllqUX6dglcGUunPmQtuMNVceXzObYG xhscXYycHBICJhI3Tl9khLDFJC7cW8/WxcjFISSwlFHi//tlrBDOV0aJGU9fsIJUsQlYSUxs XwXWISKgI/F4Tg8jSBGzwHomiY3vd4ElhAViJDbdn8UCYrMIqEocuN8E1MzBwSugKbH8ohxI WFTAS6Jn+yOwck4BbYnmxu+MEMsWMUrM+ngYrJdXQFDix+R7YDazgLzEvv1TWSFsLYn1O48z TWAUmIWkbBaSsllIyhYwMq9ilEgtSC4oTkrPNcpLLdcrTswtLs1L10vOz93ECI6NZ9I7GA/v cj/EKMDBqMTDuyCnNlyINbGsuDL3EKMEB7OSCK+2WV24EG9KYmVValF+fFFpTmrxIUZpDhYl cd7H/9eFCQmkJ5akZqemFqQWwWSZODilGhjtoiQ1/H9kpKW9lDw0n6P6xYJV2rcslNKFPONe XPy5VezklFCL7Y9Tjs2UmufydL7suytb55bmTv684Ixqeljaj/Du/6FTAiU+fN0/S+OVjN/G gxM0V3KxCS8oWX9YulCcu/n9vqKt9xfXnrueuVLN+daaVYkaf5+/VQtUyV7R8GTTs0eLdpTM V2Ipzkg01GIuKk4EAGbczDyJAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi On Thursday, July 07, 2016 12:45:57 PM Sylwester Nawrocki wrote: > On 07/05/2016 10:29 PM, Abhilash Kesavan wrote: > > Exynos7 has the same CPU clock registers layout as that present Please precise for which Exynos7 SoC this change is needed (all three of them?). > > in Exynos5433 except for the bits in the MUX_STAT* registers. > > Add a new CLK_CPU_HAS_MODIFIED_MUX_STAT flag to handle this change. > > > --- a/drivers/clk/samsung/clk-cpu.h > > +++ b/drivers/clk/samsung/clk-cpu.h > > @@ -63,6 +63,8 @@ struct exynos_cpuclk { > > /* The CPU clock registers have Exynos5433-compatible layout */ > > #define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) > > > +/* Exynos5433-compatible layout with different MUX_STAT register bits */ > > +#define CLK_CPU_HAS_MODIFIED_MUX_STAT (1 << 3) > > It's getting a bit messy, what if there comes another SoC version > which has some other modification of exynos5433 registers structure? > We would need another variant of HAS_MODIFIED_MUX_STAT flag and we > could easily get lost while trying to determine which modification > is which. How about indicating explicitly it's an exynos7 bits > layout and renaming the flag to something like > > #define CLK_CPU_HAS_E7_MUX_STAT (1 << 16) ? ditto Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics