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x-ms-exchange-antispam-messagedata: 0z/9iDby6r1RomoUT3gx21JWxqrI3EYVWQLLFJi8jVtrhXxxYhJos+kiyjBaBuEbINB7Yut+1BS7RYLATStFiQVB9Hin/yGEDQyngsglkEtxCWTVWVi4YKOGQuoGnb8vuUit3LGMWu+PqKJDElC6o+7yDUXIlDZpl+VhBVhekW5ZKRH+BQ49coEQQAwSekBerkdd2FHBG53rPS7ajcOoTPhYgQOnJ8dQHomtZWqg66ncY370sDG7HP/7JksGO+tF0k9iu4FUY7ouza4eHorXs1HPwyH/2AyYa7HWSAogyeskJYgVLBC5ve4+MgY0s6xh+Bt22Q+8vqguJOTtvs/4VMAP1F8bzIB02UuUT6uaOfSCMnH6fqXBVH9gDW5BocI20gY5pNGobcCosEpocvCPajZR/Vy8jes95mJN+xFTgJPxQLAM+jC5Iyh4UOxEbfPpuxYSptFI4+zPWMpaxHRwvlEA68SdrYIYg0eG40A1Wa4= Content-Type: text/plain; charset="us-ascii" Content-ID: <44CDA89EFFB0AE4D9EC0B1C246CED218@namprd11.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: a709c7c3-0de1-4d26-de04-08d7f667c97e X-MS-Exchange-CrossTenant-originalarrivaltime: 12 May 2020 11:29:51.6335 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: z468bkByZ2ePhuJQZSoQnWSjgQw18GCKblKph7YUtgNcrIkd4qfNYzyvlkusdQlQo+RfuO6hymhUdA/Yok6xr7p3AkyyGTNx11Oj901DsjM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4273 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Vignesh, On Tuesday, May 12, 2020 12:49:07 PM EEST Vignesh Raghavendra wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know th= e > content is safe > On 12/05/20 11:46 am, Tudor.Ambarus@microchip.com wrote: > > Hi, Boris, Pratyush, > >=20 > > I stripped case 2/, we'll not treat it for now. > >=20 > > On Monday, May 11, 2020 12:27:12 PM EEST Boris Brezillon wrote: > >> EXTERNAL EMAIL: Do not click links or open attachments unless you know > >> the > >> content is safe > >>=20 > >> On Mon, 11 May 2020 09:00:35 +0000 > >>=20 > >> wrote: > >>> Hi, Pratyush, Boris, > >>>=20 > >>> On Friday, April 24, 2020 9:43:54 PM EEST Pratyush Yadav wrote: > >>>> This series adds support for octal DTR flashes in the spi-nor > >>>> framework, > >>>=20 > >>> I'm still learning about this, but I can give you my 2 cents as of no= w, > >>> to > >>> open the discussion. Enabling 2-2-2, 4-4-4, and 8-8-8 modes is danger= ous > >>> because the flash may not recover from unexpected resets. Entering on= e > >>> of > >>> these modes can be: > >>> 1/ volatile selectable, the device return to the 1-1-1 protocol after > >>> the > >>> next power-on. I guess this is conditioned by the optional RESET pin, > >>> but > >>> I'll have to check. Also the flash can return to the 1-1-1 mode using > >>> the > >>> software reset or through writing to its Configuration Register, with= out > >>> power-on or power- off. > >>=20 > >> My understanding is that there's no standard software reset procedure > >> that guarantees no conflict with existing 1S commands, so even the > >> software reset approach doesn't work here. > >=20 > > The software reset procedure can't protect you from unexpected resets, = but > > the hardware with its optional reset pin can. Pratyush to confirm. > >=20 > > cut > >=20 > >>> Not recovering from unexpected resets is unacceptable. One should alw= ays > >>> prefer option 1/ and condition the entering in 2-2-2, 4-4-4 and 8-8-8 > >>> with > >>> the presence of the optional RESET pin. > >>=20 > >> Totally agree with you on that one, but we know what happens in > >> practice... > >=20 > > What I proposed is to condition the entering in the state-full modes wi= th > > the presence of the optional RESET pin. We would introduce an optional > > device tree property for the RESET pin. If hardware doesn't implement t= he > > optional RESET# signal, then we will not enter in the state-full modes. >=20 > Are you asking for dedicated SW controllable reset line or just an > indication from DT that OSPI reset line is connected to board level > soft/hard reset lines? I don't see a need for the reset line to be SW controllable, a simple=20 indication from the device tree should be enough. >=20 > Mandating SW controllable RESET line is bit of a stretch IMO... Board > design may not allow wasting dedicated pin due to lack of GPIOs perhaps.. >=20 > For eg.: TI EVM has OSPI reset line connected to board level reset out. > This ensures any soft/warm/hard CPU reset will trigger OSPI Flash reset, > but there is no SW control that allows OSPI flash alone to be reset. > Isn't such a reset mechanism sufficient? >=20 I think it is, yes. Cheers, ta