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November 2026, 21:11:56 Mitteleurop=C3=A4ische Normalzeit sc= hrieb Coia Prant: > Heiko Stuebner =E4=BA=8E2026=E5=B9=B411=E6=9C=881=E6=97= =A5=E5=91=A8=E6=97=A5 22:06=E5=86=99=E9=81=93=EF=BC=9A > > > > Hi, > > > > Am Freitag, 23. Oktober 2026, 07:35:46 Mitteleurop=C3=A4ische Normalzei= t schrieb Coia Prant: > > > The RK3568 SoC integrates a Synopsys DesignWare XPCS that provides > > > the Physical Coding Sublayer for 1000BASE-X, SGMII, and QSGMII > > > interfaces via its four MII ports. Add the XPCS device node to the > > > SoC device tree. > > > > > > The XPCS device is accessed via the APB3 bus at 0xfda00000 and > > > requires the CSR clock (PCLK_XPCS) for register access and the EEE > > > clock (CLK_XPCS_EEE) for Energy Efficient Ethernet operation. The > > > PD_PIPE power domain must be enabled before any register access. > > > > > > Also add two fixed-clock nodes (clock-xpcs-gmac0 and clock-xpcs-gmac1, > > > labelled clk_gmac0_xpcs_mii and clk_gmac1_xpcs_mii) providing the > > > 125 MHz reference clock for the GMACs when operating with XPCS. Their > > > clock-output-names match the CRU mux parent names in clk-rk3568.c, so > > > boards can reparent SCLK_GMAC0_RX_TX / SCLK_GMAC1_RX_TX through > > > assigned-clock-parents. > > > > > > The XPCS node is disabled by default and must be enabled at the board > > > level when 1000BASE-X/SGMII/QSGMII is in use. The fixed-clock nodes > > > are always present and do not have a status property, as they are > > > static clock sources. > > > > > > The XPCS node requires a reference to the appropriate Naneng Combo PHY > > > via the phys property. dtbs_check only validates required properties > > > for enabled nodes, so the SoC dtsi does not provide phys: boards that > > > enable the XPCS must supply it, since the SerDes link is a board-level > > > design choice (combphy1 on some boards, combphy2 on others). > > > > > > Signed-off-by: Coia Prant > > > --- > > > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 23 +++++++++++++++++++++++ > > > 1 file changed, 23 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3568.dtsi > > > index 3bc653f027f1f..20a72785adbc2 100644 > > > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > > @@ -8,6 +8,20 @@ > > > / { > > > compatible =3D "rockchip,rk3568"; > > > > > > + clk_gmac0_xpcs_mii: clock-xpcs-gmac0 { > > > + compatible =3D "fixed-clock"; > > > + clock-frequency =3D <125000000>; > > > + clock-output-names =3D "clk_gmac0_xpcs_mii"; > > > + #clock-cells =3D <0>; > > > + }; > > > + > > > + clk_gmac1_xpcs_mii: clock-xpcs-gmac1 { > > > + compatible =3D "fixed-clock"; > > > + clock-frequency =3D <125000000>; > > > + clock-output-names =3D "clk_gmac1_xpcs_mii"; > > > + #clock-cells =3D <0>; > > > + }; > > > + > > > > these clocks don't belong here. > > > > When you place these nodes in the main, they seem to come out of > > thin air, while that might be true for some boards, that they > > have dedicated oscillators for that, this will likely not be true > > for all. > > > > So these should be defined in the board dts, to match the actual > > hardware. > > > > > > Heiko > > >=20 > Hi Heiko, >=20 > Okay, these are board-level clock sources, not something the SoC > provides. Moving both fixed-clock nodes to the Photonicat DTS and > leaving only the xpcs node in rk3568.dtsi. >=20 > I'll respin. please also at least describe in the commit message, where the board generates these clocks. Thanks Heiko