From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964907AbdJRMML (ORCPT ); Wed, 18 Oct 2017 08:12:11 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:12766 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755159AbdJRMMJ (ORCPT ); Wed, 18 Oct 2017 08:12:09 -0400 Subject: Re: [PATCH 1/2] PCI: dwc: dra7xx: Create functional dependency between PCIe and PHY To: Roger Quadros , Bjorn Helgaas References: <20171009090338.26033-1-kishon@ti.com> <20171009090338.26033-2-kishon@ti.com> <9dce2e30-a245-460d-a808-a733eaf7ffec@ti.com> CC: , , , From: Kishon Vijay Abraham I Message-ID: <2375dfac-b68c-4a94-89ed-fb850ba5579f@ti.com> Date: Wed, 18 Oct 2017 17:42:05 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <9dce2e30-a245-460d-a808-a733eaf7ffec@ti.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Tuesday 10 October 2017 01:29 PM, Roger Quadros wrote: > On 10/10/17 10:42, Kishon Vijay Abraham I wrote: >> Roger, >> >> On Tuesday 10 October 2017 12:49 PM, Roger Quadros wrote: >>> On 09/10/17 12:03, Kishon Vijay Abraham I wrote: >>>> PCI core access configuration space registers in resume_noirq callbacks. >>>> In the case of dra7xx, PIPE3 PHY connected to PCIe controller has to be >>>> enabled before accessing configuration space registers. Since >>>> PIPE3 PHY is enabled by only configuring control module registers, no >>>> aborts has been observed so far (though during noirq stage, interface >>>> clock of PIPE3 PHY is not enabled). >>>> >>>> With new TRM updates, PIPE3 PHY has to be initialized (PIPE3 PHY >>>> registers has to be accessed) as well which requires the interface >>>> clock of PIPE3 PHY to be enabled. The interface clock of PIPE3 PHY is >>>> derived from OCP2SCP and hence PCIe PHY is modeled as a child of >>>> OCP2SCP. Since pm_runtime is not enabled during noirq stage, >>>> pm_runtime_get_sync done in phy_init doesn't enable >>>> OCP2SCP clocks resulting in abort when PIPE3 PHY registers are >>>> accessed. >>> >>> This could be the case not only with PCIe but even with USB and SATA? >> >> right, if USB/SATA driver has no_irq callbacks then the same issue might occur. > > OK. Is this something that we should document in Documentation/phy.txt? Yeah it could be but the dependency is not required for a lot of phy consumer drivers. Do you think it makes sense to create functional dependency between phy and it's consumers in phy_get? Thanks Kishon