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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bcceab592sm28864985b3a.58.2025.08.12.01.32.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Aug 2025 01:32:50 -0700 (PDT) Message-ID: <23e28eba-3c7e-439e-88d8-998decd2b285@oss.qualcomm.com> Date: Tue, 12 Aug 2025 16:32:43 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/3] Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20250714082110.3890821-1-ziyue.zhang@oss.qualcomm.com> Content-Language: en-US From: Ziyue Zhang In-Reply-To: <20250714082110.3890821-1-ziyue.zhang@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA5MDAyNyBTYWx0ZWRfX+8MhTRj+3rkX gp5AUWyhNp/CtxF34fAJ931Jyd2YR+741PvVF0IbZ4Qddz7Wn88Z7XcN8DalCt6vFdRJbWEcRpO 21wV9+CUPEc7AncUcIcDlEBxZU/VWkOi+nfXJjkq2xW0RyyffifuMJJrdczZiQcp+bQYraR+A4J p/n5fpaH9W7I+/mosKtowhtOKGzNPl8hltQ+Ueg/FA2MvDUBGo8Ti2beppO6FH8BqIVo/ZnRW1B QHCLMYi9nkQIOXAvF5RW4Zru7yK27W2R7ddqHLY8FAYSEm+DwibuCxIbIKtu4Lucp5EUruJ9MP8 Y2rOdLGpc5nazUXmFEXZN53r8qtnXMPEgNN2BFMvIlp1hplSJWUSgmaIxxWMaqsFRGJju8xQCIb sdzirBOQ X-Authority-Analysis: v=2.4 cv=fvDcZE4f c=1 sm=1 tr=0 ts=689afc34 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=JG0w1mhhnlL07z4zywYA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: -fJHZf515kWC1d7GjBpRkL3QJm0oq9SU X-Proofpoint-GUID: -fJHZf515kWC1d7GjBpRkL3QJm0oq9SU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_04,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 spamscore=0 suspectscore=0 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508090027 On 7/14/2025 4:21 PM, Ziyue Zhang wrote: > This series adds add equalization settings for 8.0 GT/s, and add PCIe lane equalization > preset properties for 8.0 GT/s and 16.0 GT/s for sa8775p ride platform, which fix AER > errors. > > While equalization settings for 16 GT/s have already been set, this update adds the > required equalization settings for PCIe operating at 8.0 GT/s, including the > configuration of shadow registers, ensuring optimal performance and stability. > > The DT change for sa8775p add PCIe lane equalization preset properties for 8 GT/s > and 16 GT/s data rates used in lane equalization procedure. > > Signed-off-by: Ziyue Zhang > > Changes in v4: > - Bail out early if the link speed > 16 GT/s and use pci->max_link_speed directly (Mani) > - Fix the build warning. (Bjorn) > - Link to v3: https://lore.kernel.org/all/8ccd3731-8dbc-4972-a79a-ba78e90ec4a8@quicinc.com/ > > Changes in v3: > - Delte TODO tag and warn print in pcie-qcom-common.c. (Bjorn) > - Refined the commit message for better readability. (Bjorn) > - Link to v2: https://lore.kernel.org/all/20250611100319.464803-1-quic_ziyuzhan@quicinc.com/ > > Changes in v2: > - Update code in pcie-qcom-common.c make it easier to read. (Neil) > - Fix the compile error. > - Link to v1: https://lore.kernel.org/all/20250604091946.1890602-1-quic_ziyuzhan@quicinc.com > > > Ziyue Zhang (3): > PCI: qcom: Add equalization settings for 8.0 GT/s > PCI: qcom: fix macro typo for CURSOR > arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset > properties > > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 +++ > drivers/pci/controller/dwc/pcie-designware.h | 5 +- > drivers/pci/controller/dwc/pcie-qcom-common.c | 54 ++++++++++--------- > drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +-- > drivers/pci/controller/dwc/pcie-qcom.c | 6 +-- > 6 files changed, 45 insertions(+), 34 deletions(-) > > > base-commit: 58ba80c4740212c29a1cf9b48f588e60a7612209 Hi Maintainers, It seems the patches get reviewed tag for a long time, can you give this series further comment or help me to merge them ? Thanks very much. BRs Ziyue