From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933480AbcHDLOs (ORCPT ); Thu, 4 Aug 2016 07:14:48 -0400 Received: from mout.kundenserver.de ([212.227.17.10]:63707 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933061AbcHDLOp (ORCPT ); Thu, 4 Aug 2016 07:14:45 -0400 From: Arnd Bergmann To: Kishon Vijay Abraham I Cc: Joao Pinto , "bhelgaas@google.com" , "linux-pci@vger.kernel.org" , Jingoo Han , Pratyush Anand , Ley Foon Tan , Rob Herring , Tanmay Inamdar , Roy Zang , Mingkai Hu , Minghuan Lian , Richard Zhu , Lucas Stach , Murali Karicheri , Thomas Petazzoni , Jason Cooper , Thierry Reding , Simon Horman , Zhou Wang , Gabriele Paoloni , Stanimir Varbanov , David Daney , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-omap@vger.kernel.org" , Carlos Palminha Subject: Re: Support for configurable PCIe endpoint Date: Thu, 04 Aug 2016 13:13:06 +0200 Message-ID: <2422602.ltmdGR0pWX@wuerfel> User-Agent: KMail/5.1.3 (Linux/4.4.0-31-generic; KDE/5.18.0; x86_64; ; ) In-Reply-To: <57A31299.2040805@ti.com> References: <57A18927.9070003@ti.com> <7c696488-eb78-d6d9-dc70-49fa5b4e3317@synopsys.com> <57A31299.2040805@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:VYHV3hGNos7V49KQE9mw4yFauEe7vZWusqo3JAYReCBQWtqSwiC hEUEEE7nv0DgK8LgmewnMc2XMngPjZ5RkcbzsXLSTnzHFV3qRJfi87GT4OzZTd4bNhSQFWa UV8N6S8ZU70zey9k6a68vOY8ojsqSQt7+eXDOz6wHIJSS5/qvH1FtebFrOPu1lrpgX5qL96 ro7qM71ny/kIFxCfep0yg== X-UI-Out-Filterresults: notjunk:1;V01:K0:oye7Ux6LMv4=:+860FHwismNgDmXH2fNBB+ djkq5JTB6WptoKa983yrRdZLfdW4OSELpyt231YRkoBtY3RW5oWetB+ADxgozpAH5Ajz8yH4V ye69Yv/8INRF2bFh0ombofPBZbJM6Um83YlB5lYQ/NHp74yQe1yO37iF886pXOURnP8J8BPmQ mJPtI7kOeU8aGFG/0oKANsg6enYAT/1WTK3oomFNdbPjvUEzqz4VEv53JUeKQd0DAIjmIHvaE PFHMnq6jEMGFnm12SxIRrbuta8EcZeBBfo9pJC7srDNE2MGYM7lP2EdLzc65Uif69XAVZo17k eLug9Ro3ELBSl2wqs5j8938Qa17wBjAes4OSyfzdjUx150zWBvb3Q/C/MPZbtKPzELd8g5rL9 eY9TgBSXwgyiQlHsiiv7x8bxBDZagzugQXOCtC44B2SObbEEfIvrXTDTij5utrUQJtU4QQ+bx 2iXFVmoaNFblByQLkW5G8IeuIrGZuoeZSp7bFx/op8rayM/9FMqFAELZBeUOZfKbrc1owMGrk gJC5hrFfJ/wd+DwpKJ9Swl3R4OTTU/rEYbpTMIYNF7poyaQh36c2/6bTlLNXoZ0W9ixt7mcxO i5e1M6ISM1hWHZiEjszHRzEzmLTh/gWWz7klvmaxEZoC9VX8ApKFS6Wjs0+buVAahANWPKbCQ FljjPaR8bsIRAZffVtYS/gU0Kad7nhbRhfHv5vEuOE1aCVT5+3zDl0nAMwSyNn3LBDertSCr+ O3O3dRlhqEyNLHet Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday, August 4, 2016 3:32:01 PM CEST Kishon Vijay Abraham I wrote: > On Wednesday 03 August 2016 07:09 PM, Joao Pinto wrote: > > > > You are rising a topic that we are also addressing in Synopsys. > > > > For the PCIe RC hardware validation we are currently using the standard > > pcie-designware and pcie-designware-plat drivers. > > > > For the Endpoint we have to use an internal software package. Its main purpose > > is to initialize the IP registers, eDMA channels and make data transfer to prove > > that the everything is working properly. This is done in 2 levels, a custom > > driver built and loaded and an application that makes some ioctl to the driver > > executing some interesting functions to check the Endpoint status and make some > > data exchange. > > hmm.. the platform I have doesn't have a DMA in PCIe IP > (http://www.ti.com/lit/ug/spruhz6g/spruhz6g.pdf). So in your testing does the > EP access RC memory? i.e the driver in the RC allocates memory from it's DDR > and gives it's DDR address to the EP. The EP then transfers data to this > address. (This is a typical use case with ethernet PCIe cards). IIUC that's not > simple with configurable EPs. I'd like to know more about your testing though. What's the difference between using the EDMA on that chip or a DMA engine that is part of the PCIe bridge? Arnd