From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2788207A2C for ; Thu, 10 Apr 2025 07:16:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744269389; cv=none; b=LDB63y9xbdgcBQNDkghO4yXh1yVIGJFCDB25z15AmkkVizNGT6tONKSiE8sXLjuRt1eS1TEW4KVIRXNzQADFuAYux95CpKMME3Pw4iS0fMHqsO4qm3r9jbnzdKsufYMw+FcnMCamWPqVKauBP7etHFMYOrYeWMKc0v6GrxCMHJE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744269389; c=relaxed/simple; bh=R4kkkcVVHPzCslI6+XyVJA1Y1Bm2lhw2qswzN6HQ8vk=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=BNxt6nLj8fKQJmzHWJ8cnScCU8+KFHATuxxz1+PwrCarg3kZV/gZ84qIo5SvBPs1j0Xa639f2t57X1Q2xCdyyczy0w6wyrxMAnvplBbF+32DjZ4mPcf+ULdzXCGjFYhbj4fflQaEYWGdZmlX00SkuqRWbCAGL1dkijNVWrgARTA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eptIZUAl; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eptIZUAl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744269388; x=1775805388; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=R4kkkcVVHPzCslI6+XyVJA1Y1Bm2lhw2qswzN6HQ8vk=; b=eptIZUAlrf6iNQmTTJrhK+9Mu/42nkCCbjvXEQjRMhJdXFBpAXB3eTKo J+EKcAWJ93jtYR5IrhbdjL5rMxjsEhFPGAh4LOdmO0XpXluzv4aBMPn6t STfdhCPNImMS37NO5hkHoLaAxEWuKZJODxbC5sX/W3HQ7n7W2pHcKMdYl kBVI+gT5V5ekafvF/vxHGpgGEYnM33DrrOcWpKyP+vR+rigS1OLNFi7WR AP0TiYJWYzOsHTAMzE/YiP5Fn+SuqAJ7VJDCvtVtSimkWQjnXk8+N6GkH PswJMcwhrj+drH7Uf6djr1c+X8lUcToCdoolTshrEO4Lmi0fg5tRBpPHv Q==; X-CSE-ConnectionGUID: W6+aUR1ITUqX8APbZqAFZw== X-CSE-MsgGUID: 43silI2pSNqgd0ZjnIFCPg== X-IronPort-AV: E=McAfee;i="6700,10204,11399"; a="49612962" X-IronPort-AV: E=Sophos;i="6.15,202,1739865600"; d="scan'208";a="49612962" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2025 00:16:27 -0700 X-CSE-ConnectionGUID: AmHfHo1fRUGdHcMQwo/88g== X-CSE-MsgGUID: bnLX8qyeRGWb5DOIaJhyUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,202,1739865600"; d="scan'208";a="133788870" Received: from kwywiol-mobl1.ger.corp.intel.com (HELO [10.245.83.152]) ([10.245.83.152]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2025 00:16:25 -0700 Message-ID: <2435f0f1-fef4-4c7c-8584-55d5480ca245@linux.intel.com> Date: Thu, 10 Apr 2025 09:16:22 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V1] accel/amdxdna: Fix incorrect size of ERT_START_NPU commands To: Lizhi Hou , ogabbay@kernel.org, quic_jhugo@quicinc.com, dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, min.ma@amd.com, max.zhen@amd.com, sonal.santan@amd.com, king.tam@amd.com References: <20250409210013.10854-1-lizhi.hou@amd.com> Content-Language: en-US From: Jacek Lawrynowicz Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298 Gdansk - KRS 101882 - NIP 957-07-52-316 In-Reply-To: <20250409210013.10854-1-lizhi.hou@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Reviewed-by: Jacek Lawrynowicz On 4/9/2025 11:00 PM, Lizhi Hou wrote: > When multiple ERT_START_NPU commands are combined in one buffer, the > buffer size calculation is incorrect. Also, the condition to make sure > the buffer size is not beyond 4K is also fixed. > > Fixes: aac243092b70 ("accel/amdxdna: Add command execution") > Signed-off-by: Lizhi Hou > --- > drivers/accel/amdxdna/aie2_message.c | 6 +++--- > drivers/accel/amdxdna/aie2_msg_priv.h | 10 ++++------ > 2 files changed, 7 insertions(+), 9 deletions(-) > > diff --git a/drivers/accel/amdxdna/aie2_message.c b/drivers/accel/amdxdna/aie2_message.c > index bf4219e32cc1..82412eec9a4b 100644 > --- a/drivers/accel/amdxdna/aie2_message.c > +++ b/drivers/accel/amdxdna/aie2_message.c > @@ -525,7 +525,7 @@ aie2_cmdlist_fill_one_slot_cf(void *cmd_buf, u32 offset, > if (!payload) > return -EINVAL; > > - if (!slot_cf_has_space(offset, payload_len)) > + if (!slot_has_space(*buf, offset, payload_len)) > return -ENOSPC; > > buf->cu_idx = cu_idx; > @@ -558,7 +558,7 @@ aie2_cmdlist_fill_one_slot_dpu(void *cmd_buf, u32 offset, > if (payload_len < sizeof(*sn) || arg_sz > MAX_DPU_ARGS_SIZE) > return -EINVAL; > > - if (!slot_dpu_has_space(offset, arg_sz)) > + if (!slot_has_space(*buf, offset, arg_sz)) > return -ENOSPC; > > buf->inst_buf_addr = sn->buffer; > @@ -569,7 +569,7 @@ aie2_cmdlist_fill_one_slot_dpu(void *cmd_buf, u32 offset, > memcpy(buf->args, sn->prop_args, arg_sz); > > /* Accurate buf size to hint firmware to do necessary copy */ > - *size += sizeof(*buf) + arg_sz; > + *size = sizeof(*buf) + arg_sz; > return 0; > } > > diff --git a/drivers/accel/amdxdna/aie2_msg_priv.h b/drivers/accel/amdxdna/aie2_msg_priv.h > index 4e02e744b470..6df9065b13f6 100644 > --- a/drivers/accel/amdxdna/aie2_msg_priv.h > +++ b/drivers/accel/amdxdna/aie2_msg_priv.h > @@ -319,18 +319,16 @@ struct async_event_msg_resp { > } __packed; > > #define MAX_CHAIN_CMDBUF_SIZE SZ_4K > -#define slot_cf_has_space(offset, payload_size) \ > - (MAX_CHAIN_CMDBUF_SIZE - ((offset) + (payload_size)) > \ > - offsetof(struct cmd_chain_slot_execbuf_cf, args[0])) > +#define slot_has_space(slot, offset, payload_size) \ > + (MAX_CHAIN_CMDBUF_SIZE >= (offset) + (payload_size) + \ > + sizeof(typeof(slot))) > + > struct cmd_chain_slot_execbuf_cf { > __u32 cu_idx; > __u32 arg_cnt; > __u32 args[] __counted_by(arg_cnt); > }; > > -#define slot_dpu_has_space(offset, payload_size) \ > - (MAX_CHAIN_CMDBUF_SIZE - ((offset) + (payload_size)) > \ > - offsetof(struct cmd_chain_slot_dpu, args[0])) > struct cmd_chain_slot_dpu { > __u64 inst_buf_addr; > __u32 inst_size;