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Just be careful to keep the same tabs vs spaces style as the nearby code. Thanks! Mathieu > > diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig > index 5b2488142041..e96935373796 100644 > --- a/arch/arc/Kconfig > +++ b/arch/arc/Kconfig > @@ -6,6 +6,7 @@ > config ARC > def_bool y > select ARC_TIMERS > + select ARCH_HAS_CPU_CACHE_ALIASING > select ARCH_HAS_CACHE_LINE_SIZE > select ARCH_HAS_DEBUG_VM_PGTABLE > select ARCH_HAS_DMA_PREP_COHERENT > diff --git a/arch/arc/include/asm/cachetype.h b/arch/arc/include/asm/cachetype.h > new file mode 100644 > index 000000000000..acd3b6cb4bf5 > --- /dev/null > +++ b/arch/arc/include/asm/cachetype.h > @@ -0,0 +1,8 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_ARC_CACHETYPE_H > +#define __ASM_ARC_CACHETYPE_H > + > +#define cpu_dcache_is_aliasing() false > +#define cpu_icache_is_aliasing() true > + > +#endif > diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h > index 108060612bb8..61a46cdff1dc 100644 > --- a/include/linux/cacheinfo.h > +++ b/include/linux/cacheinfo.h > @@ -155,8 +155,14 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level) > > #ifndef CONFIG_ARCH_HAS_CPU_CACHE_ALIASING > #define cpu_dcache_is_aliasing() false > +#define cpu_icache_is_aliasing() cpu_dcache_is_aliasing() > #else > #include > + > +#ifndef cpu_icache_is_aliasing > +#define cpu_icache_is_aliasing() cpu_dcache_is_aliasing() > +#endif > + > #endif > > #endif /* _LINUX_CACHEINFO_H */ > > > Best Regards, > Yan, Zi -- Mathieu Desnoyers EfficiOS Inc. https://www.efficios.com