From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932316AbdJWP1q convert rfc822-to-8bit (ORCPT ); Mon, 23 Oct 2017 11:27:46 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:15690 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932166AbdJWP1o (ORCPT ); Mon, 23 Oct 2017 11:27:44 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 23 Oct 2017 08:27:13 -0700 Subject: Re: [RFC PATCH 3/3] mm/map_contig: Add mmap(MAP_CONTIG) support To: Michal Hocko , Christopher Lameter CC: Guy Shattah , Mike Kravetz , , , , Marek Szyprowski , Michal Nazarewicz , "Aneesh Kumar K . V" , Joonsoo Kim , Anshuman Khandual , Laura Abbott , Vlastimil Babka References: <20171013152801.nbpk6nluotgbmfrs@dhcp22.suse.cz> <20171013154747.2jv7rtfqyyagiodn@dhcp22.suse.cz> <20171013161736.htumyr4cskfrjq64@dhcp22.suse.cz> <752b49eb-55c6-5a34-ab41-6e91dd93ea70@mellanox.com> <20171016082456.no6ux63uy2rmj4fe@dhcp22.suse.cz> <0e238c56-c59d-f648-95fc-c8cb56c3652e@mellanox.com> <20171016123248.csntl6luxgafst6q@dhcp22.suse.cz> <20171016174229.pz3o4uhzz3qbrp6n@dhcp22.suse.cz> From: David Nellans Message-ID: <2447359e-6d22-4fdc-c48a-3912bfbb69b7@nvidia.com> Date: Mon, 23 Oct 2017 10:25:07 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20171016174229.pz3o4uhzz3qbrp6n@dhcp22.suse.cz> X-Originating-IP: [10.20.174.29] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL103.nvidia.com (172.20.187.11) Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/16/2017 12:42 PM, Michal Hocko wrote: > On Mon 16-10-17 11:00:19, Cristopher Lameter wrote: >> On Mon, 16 Oct 2017, Michal Hocko wrote: >>> That being said, the list is far from being complete, I am pretty sure >>> more would pop out if I thought more thoroughly. The bottom line is that >>> while I see many problems to actually implement this feature and >>> maintain it longterm I simply do not see a large benefit outside of a >>> very specific HW. >> There is not much new here in terms of problems. The hardware that >> needs this seems to become more and more plentiful. That is why we need a >> generic implementation. > It would really help to name that HW and other potential usecases > independent on the HW because I am rather skeptical about the > _plentiful_ part. And so I really do not see any foundation to claim > the generic part. Because, fundamentally, it is the HW which requires > the specific memory placement/physically contiguous range etc. So the > generic implementation doesn't really make sense in such a context. > There are TLB's in AMD Xen that can take advantage of contig memory to improve TLB coverage.  AFAIK contig is not functionally required, its purely a performance optimization.  Current Xen TLB implementation doesn't support arbitrary contig lengths, page sizes, etc, but its a start.  This type of TLB optimization can be handled on the back end by de-fragging phys mem (when possible) now that both base and THPs can be easily migrated; no need for up-front contig, but defrag isn't free either.