Re: [PATCH v3 2/2] nvmem: airoha: Add support for SMC eFUSE

[Srinivas Kandagatla <srini@kernel.org>]

On 5/18/26 3:20 PM, Christian Marangi wrote:
> Add support for SMC eFUSE on AN7581 SoC. The SoC have 2 set of 2048 bits of
> eFUSE that are used to read calibration value for PCIe, Thermal, USB and
> other specific info of the SoC like revision and HW device present.
> 
> eFuse value are taken by sending SMC command. ATF is responsible of
> validaing the data and rejecting reading protected data (like Private
> Key). In such case the SMC command will return non-zero value on a0
> register.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
>  drivers/nvmem/Kconfig             |  13 ++++
>  drivers/nvmem/Makefile            |   2 +
>  drivers/nvmem/airoha-smc-efuses.c | 118 ++++++++++++++++++++++++++++++
>  3 files changed, 133 insertions(+)
>  create mode 100644 drivers/nvmem/airoha-smc-efuses.c
> 
> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> index 74ddbd0f79b0..95a399258538 100644
> --- a/drivers/nvmem/Kconfig
> +++ b/drivers/nvmem/Kconfig
> @@ -28,6 +28,19 @@ source "drivers/nvmem/layouts/Kconfig"
>  
>  # Devices
>  
> +config NVMEM_AIROHA_SMC_EFUSES
> +	tristate "Airoha SMC eFuse support"
> +	depends on ARCH_AIROHA || COMPILE_TEST
> +	depends on HAVE_ARM_SMCCC
> +	default ARCH_AIROHA
> +	help
> +	  Say y here to enable support for reading eFuses on Airoha AN7581
> +	  SoCs. These are e.g. used to store factory programmed
> +	  calibration data required for the PCIe or the USB-C PHY or Thermal.
> +
> +	  This driver can also be built as a module. If so, the module will
> +	  be called nvmem-airoha-smc-efuses.
> +
>  config NVMEM_AN8855_EFUSE
>  	tristate "Airoha AN8855 eFuse support"
>  	depends on COMPILE_TEST
> diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
> index 7252b8ec88d4..f6f2bc51dee1 100644
> --- a/drivers/nvmem/Makefile
> +++ b/drivers/nvmem/Makefile
> @@ -10,6 +10,8 @@ nvmem_layouts-y			:= layouts.o
>  obj-y				+= layouts/
>  
>  # Devices
> +obj-$(CONFIG_NVMEM_AIROHA_SMC_EFUSES)	+= nvmem-airoha-smc-efuses.o
> +nvmem-airoha-smc-efuses-y 		:= airoha-smc-efuses.o
>  obj-$(CONFIG_NVMEM_AN8855_EFUSE)	+= nvmem-an8855-efuse.o
>  nvmem-an8855-efuse-y 			:= an8855-efuse.o
>  obj-$(CONFIG_NVMEM_APPLE_EFUSES)	+= nvmem-apple-efuses.o
> diff --git a/drivers/nvmem/airoha-smc-efuses.c b/drivers/nvmem/airoha-smc-efuses.c
> new file mode 100644
> index 000000000000..bb279d149519
> --- /dev/null
> +++ b/drivers/nvmem/airoha-smc-efuses.c
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + *  Author: Christian Marangi <ansuelsmth@gmail.com>
> + */
> +
> +#include <linux/arm-smccc.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/nvmem-provider.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +
> +#define AIROHA_SMC_EFUSE_FID		0x82000001
> +#define AIROHA_SMC_EFUSE_SUB_ID_READ	0x44414552
> +
> +#define AIROHA_EFUSE_CELLS		64
> +
> +struct airoha_efuse_bank_priv {
> +	u8 bank_index;
> +};
> +
> +static int airoha_efuse_read(void *context, unsigned int offset,
> +			     void *val, size_t bytes)
> +{
> +	struct regmap *regmap = context;
> +
> +	return regmap_bulk_read(regmap, offset,
> +				val, bytes / sizeof(u32));
> +}
> +
> +static int airoha_efuse_reg_read(void *context, unsigned int offset,
> +				 unsigned int *val)
> +{
> +	struct airoha_efuse_bank_priv *priv = context;
> +	struct arm_smccc_res res;
> +
> +	arm_smccc_1_1_invoke(AIROHA_SMC_EFUSE_FID,
> +			     AIROHA_SMC_EFUSE_SUB_ID_READ,
> +			     priv->bank_index, offset, 0, 0, 0, 0, &res);
> +
> +	/* check if SMC reported an error */
> +	if (res.a0)
> +		return -EIO;
> +
> +	*val = res.a1;
> +	return 0;
> +}
> +
> +static const struct regmap_config airoha_efuse_regmap_config = {
> +	.reg_read = airoha_efuse_reg_read,
> +	.reg_bits = 32,
> +	.val_bits = 32,
> +	.reg_stride = 4,
> +};
> +
> +static int airoha_efuse_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	int ret;
> +
> +	for_each_child_of_node_scoped(dev->of_node, child) {
> +		struct nvmem_config airoha_nvmem_config = {
> +			.name = "airoha-efuse",
> +			.size = AIROHA_EFUSE_CELLS * sizeof(u32),
> +			.stride = sizeof(u32),
> +			.word_size = sizeof(u32),
> +			.reg_read = airoha_efuse_read,
> +		};
> +		struct airoha_efuse_bank_priv *priv;
> +		struct nvmem_device *nvmem;
> +		struct regmap *regmap;
> +		u32 bank;
> +
> +		ret = of_property_read_u32(child, "reg", &bank);
> +		if (ret)
> +			return ret;
> +
> +		priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +		if (!priv)
> +			return -ENOMEM;
> +
> +		priv->bank_index = bank;

bank is 32 bit value now stored in 8 bit variable.

can we make bank_index 32 bit wide?