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Wed, 25 Sep 2024 20:38:59 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48PKcwdb025853 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Sep 2024 20:38:58 GMT Received: from [10.134.70.212] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 13:38:55 -0700 Message-ID: <24a11f4c-d848-4f1b-afbd-35b135fa3105@quicinc.com> Date: Wed, 25 Sep 2024 13:38:51 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/22] drm/msm/dpu: move resource allocation to CRTC To: Dmitry Baryshkov CC: Rob Clark , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , , , , , , Rob Clark , =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= References: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> <20240924-concurrent-wb-v2-5-7849f900e863@quicinc.com> Content-Language: en-US From: Jessica Zhang In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: HQfy6X8dyIuenG609UO1FYSJh9K-t1tf X-Proofpoint-GUID: HQfy6X8dyIuenG609UO1FYSJh9K-t1tf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409250147 On 9/24/2024 4:13 PM, Dmitry Baryshkov wrote: > On Tue, Sep 24, 2024 at 03:59:21PM GMT, Jessica Zhang wrote: >> From: Dmitry Baryshkov >> >> All resource allocation is centered around the LMs. Then other blocks >> (except DSCs) are allocated basing on the LMs that was selected, and LM >> powers up the CRTC rather than the encoder. >> >> Moreover if at some point the driver supports encoder cloning, >> allocating resources from the encoder will be incorrect, as all clones >> will have different encoder IDs, while LMs are to be shared by these >> encoders. >> >> Signed-off-by: Dmitry Baryshkov >> [quic_abhinavk@quicinc.com: Refactored resource allocation for CDM] >> Signed-off-by: Abhinav Kumar >> [quic_jesszhan@quicinc.com: Changed to grabbing exising global state] >> Signed-off-by: Jessica Zhang >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 86 ++++++++++++ >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 201 +++++++++++----------------- >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 19 +++ >> 3 files changed, 183 insertions(+), 123 deletions(-) >> >> @@ -544,159 +542,117 @@ void dpu_encoder_helper_split_config( >> } >> } >> >> -bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) >> +void dpu_encoder_update_topology(struct drm_encoder *drm_enc, >> + struct msm_display_topology *topology, >> + struct drm_atomic_state *state, >> + const struct drm_display_mode *adj_mode) >> { >> struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); >> - int i, intf_count = 0, num_dsc = 0; >> + struct drm_connector *connector; >> + struct drm_connector_state *conn_state; >> + struct msm_display_info *disp_info; >> + struct drm_framebuffer *fb; >> + struct msm_drm_private *priv; >> + int i; >> >> for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) >> if (dpu_enc->phys_encs[i]) >> - intf_count++; >> + topology->num_intf++; >> >> - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ >> + /* We only support 2 DSC mode (with 2 LM and 1 INTF) */ >> if (dpu_enc->dsc) >> - num_dsc = 2; >> + topology->num_dsc += 2; >> >> - return (num_dsc > 0) && (num_dsc > intf_count); >> -} >> + connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); >> + if (!connector) >> + return; >> + conn_state = drm_atomic_get_new_connector_state(state, connector); >> + if (!conn_state) >> + return; >> >> -struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) >> -{ >> - struct msm_drm_private *priv = drm_enc->dev->dev_private; >> - struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); >> - int index = dpu_enc->disp_info.h_tile_instance[0]; >> + disp_info = &dpu_enc->disp_info; >> >> - if (dpu_enc->disp_info.intf_type == INTF_DSI) >> - return msm_dsi_get_dsc_config(priv->dsi[index]); >> + priv = drm_enc->dev->dev_private; >> >> - return NULL; >> + /* >> + * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it. >> + * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check() >> + * earlier. >> + */ >> + if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) { >> + fb = conn_state->writeback_job->fb; >> + >> + if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) >> + topology->needs_cdm = true; >> + } else if (disp_info->intf_type == INTF_DP) { >> + if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode)) >> + topology->needs_cdm = true; >> + } > > Just to note, the needs_cdm is not enough once you introduce CWB > support. E.g. DP/YUV420 + WB/YUV case requires two CDM blocks (which we > don't have), but this doesn't get reflected in the topology. Hi Dmitry, Ack. I can add something to make atomic_check fail if the input FB is YUV format and CWB is enabled. Thanks, Jessica Zhang > >> } >> > -- > With best wishes > Dmitry