From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751809AbdGaLAd (ORCPT ); Mon, 31 Jul 2017 07:00:33 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:33059 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750920AbdGaLAc (ORCPT ); Mon, 31 Jul 2017 07:00:32 -0400 Subject: Re: [PATCH 05/17] clocksource: New RISC-V SBI timer driver To: Palmer Dabbelt , yamada.masahiro@socionext.com, mmarek@suse.com, will.deacon@arm.com, peterz@infradead.org, boqun.feng@gmail.com, mingo@redhat.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, gregkh@linuxfoundation.org, jslaby@suse.com, davem@davemloft.net, mchehab@kernel.org, sfr@canb.auug.org.au, fweisbec@gmail.com, viro@zeniv.linux.org.uk, mcgrof@kernel.org, dledford@redhat.com, bart.vanassche@sandisk.com, sstabellini@kernel.org, daniel.vetter@ffwll.ch, mpe@ellerman.id.au, msalter@redhat.com, nicolas.dichtel@6wind.com, james.hogan@imgtec.com, paul.gortmaker@windriver.com, linux@roeck-us.net, heiko.carstens@de.ibm.com, schwidefsky@de.ibm.com, linux-kernel@vger.kernel.org, patches@groups.riscv.org, akpm@linux-foundation.org Cc: albert@sifive.com References: <20170711013924.22085-1-palmer@dabbelt.com> <20170711013924.22085-6-palmer@dabbelt.com> From: Daniel Lezcano Message-ID: <24a37ba4-df64-21c4-abec-18c0dbed0ab7@linaro.org> Date: Mon, 31 Jul 2017 13:00:26 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170711013924.22085-6-palmer@dabbelt.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/07/2017 03:39, Palmer Dabbelt wrote: > The RISC-V ISA defines a per-hart real-time clock and timer, which is > present on all systems. The clock is accessed via the 'rdtime' > pseudo-instruction (which reads a CSR), and the timer is set via an SBI > call. > > This driver attempts to split out the RISC-V ISA specific mechanisms of > accessing the hardware from the clocksource driver by taking a pair of > function pointers to issue the actual RISC-V specific instructions. > > Signed-off-by: Palmer Dabbelt > --- [ ... ] > +#ifndef _LINUX_TIMER_RISCV_H > +#define _LINUX_TIMER_RISCV_H > + > +/* > + * All RISC-V systems have a timer attached to every hart. These timers can be > + * read by the 'rdcycle' pseudo instruction, and can use the SBI to setup > + * events. In order to abstract the architecture-specific timer reading and > + * setting functions away from the clock event insertion code, we provide > + * function pointers to the clockevent subsystem that perform two basic operations: > + * rdtime() reads the timer on the current CPU, and next_event(delta) sets the > + * next timer event to 'delta' cycles in the future. As the timers are > + * inherently a per-cpu resource, these callbacks perform operations on the > + * current hart. There is guaranteed to be exactly one timer per hart on all > + * RISC-V systems. > + */ Hi Palmer, The driver code must be self contained (eg. setup and irq handling). There are examples in the drivers/clocksource to stick on, for example the jcore-pit.c or the mips-gic-timer.c drivers. I don't see the point to setup callbacks at init time. Thanks. -- Daniel > +void timer_riscv_init(int cpu_id, > + unsigned long riscv_timebase, > + unsigned long long (*rdtime)(struct clocksource *), > + int (*next_event)(unsigned long, struct clock_event_device *)); > + > +/* > + * Looks up the clocksource or clock_even_device that cooresponds the given > + * hart. > + */ > +struct clocksource *timer_riscv_source(int cpuid); > +struct clock_event_device *timer_riscv_device(int cpu_id); > + > +#endif > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog