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Wed, 27 Aug 2025 14:41:59 +0000 Received: from AM8PR04MB7779.eurprd04.prod.outlook.com ([fe80::7417:d17f:8d97:44d2]) by AM8PR04MB7779.eurprd04.prod.outlook.com ([fe80::7417:d17f:8d97:44d2%7]) with mapi id 15.20.9073.010; Wed, 27 Aug 2025 14:41:59 +0000 Message-ID: <24a5e0b1-592f-4e74-a938-c261c8ce8536@topic.nl> Date: Wed, 27 Aug 2025 16:41:57 +0200 User-Agent: Mozilla Thunderbird From: Mike Looijmans Subject: Re: [PATCH v2 2/2] drm: bridge: Add TI tmds181 and sn65dp159 driver To: Maxime Ripard CC: dri-devel@lists.freedesktop.org, Andrzej Hajda , David Airlie , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Maarten Lankhorst , Neil Armstrong , Robert Foss , Simona Vetter , Thomas Zimmermann , linux-kernel@vger.kernel.org References: <20250819053205.9976-1-mike.looijmans@topic.nl> <1b153bce-a66a-45ee-a5c6-963ea6fb1c82.949ef384-8293-46b8-903f-40a477c056ae.9365be0b-205e-4d59-ad18-c1924bf45277@emailsignatures365.codetwo.com> <20250819053205.9976-3-mike.looijmans@topic.nl> <5dc6mmx26aa6qoig5wkei2uozdjmx5r2uduhc5wtja7dhjdypj@fincrfpg5u3s> <7d57e55a-223f-4c3a-8806-1ea616b56d02@topic.nl> <20250825-red-bear-of-infinity-054eb7@houat> Content-Language: en-US, nl Organization: Topic In-Reply-To: <20250825-red-bear-of-infinity-054eb7@houat> Content-Type: text/plain; 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X-OriginatorOrg: topic.nl X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 14:42:02.3135 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c2ffb72-f7b7-4368-8595-08dde577e2b1 X-MS-Exchange-CrossTenant-Id: 449607a5-3517-482d-8d16-41dd868cbda3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=449607a5-3517-482d-8d16-41dd868cbda3;Ip=[20.93.157.195];Helo=[westeu11-emailsignatures-cloud.codetwo.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C713.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8387 On 25-08-2025 16:14, Maxime Ripard wrote: > On Tue, Aug 19, 2025 at 04:25:29PM +0200, Mike Looijmans wrote: >> On 19-08-2025 15:22, Maxime Ripard wrote: >>> On Tue, Aug 19, 2025 at 07:31:15AM +0200, Mike Looijmans wrote: >>>> The tmds181 and sn65dp159 are "retimers" and hence can be considered >>>> HDMI-to-HDMI bridges. Typical usage is to convert the output of an >>>> FPGA into a valid HDMI signal, and it will typically be inserted >>>> between an encoder and hdmi-connector. >>>> >>>> Signed-off-by: Mike Looijmans >>>> --- >>>> >>>> Changes in v2: >>>> Use atomic_enable/disable >>>> Use #defines for bit fields in registers >>>> Allow HDMI 2 compliance >>>> Filter modes on clock range >>>> Use cross-over pixel frequency instead of manual overides >>>> Devicetree bindings according to standards >>>> >>>> drivers/gpu/drm/bridge/Kconfig | 11 + >>>> drivers/gpu/drm/bridge/Makefile | 1 + >>>> drivers/gpu/drm/bridge/ti-tmds181.c | 561 +++++++++++++++++++++++++= +++ >>>> 3 files changed, 573 insertions(+) >>>> create mode 100644 drivers/gpu/drm/bridge/ti-tmds181.c >>>> >>>> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/K= config >>>> index b9e0ca85226a..753177fc9b50 100644 >>>> --- a/drivers/gpu/drm/bridge/Kconfig >>>> +++ b/drivers/gpu/drm/bridge/Kconfig >>>> @@ -430,6 +430,17 @@ config DRM_TI_SN65DSI86 >>>> help >>>> Texas Instruments SN65DSI86 DSI to eDP Bridge driver >>>> +config DRM_TI_TMDS181 >>>> + tristate "TI TMDS181 and SN65DP159 HDMI retimer bridge driver= " >>>> + depends on OF >>>> + select DRM_KMS_HELPER >>>> + select REGMAP_I2C >>>> + help >>>> + Enable this to support the TI TMDS181 and SN65DP159 HDMI retimers. >>>> + The SN65DP159 provides output into a cable (source) whereas the >>>> + TMDS181 is meant to forward a cable signal into a PCB (sink). Eith= er >>>> + can be set up as source or sink though. >>>> + >>>> config DRM_TI_TPD12S015 >>>> tristate "TI TPD12S015 HDMI level shifter and ESD protection" >>>> depends on OF >>>> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/= Makefile >>>> index 245e8a27e3fc..f4b5089e903c 100644 >>>> --- a/drivers/gpu/drm/bridge/Makefile >>>> +++ b/drivers/gpu/drm/bridge/Makefile >>>> @@ -39,6 +39,7 @@ obj-$(CONFIG_DRM_TI_SN65DSI83) +=3D ti-sn65dsi83.o >>>> obj-$(CONFIG_DRM_TI_SN65DSI86) +=3D ti-sn65dsi86.o >>>> obj-$(CONFIG_DRM_TI_TDP158) +=3D ti-tdp158.o >>>> obj-$(CONFIG_DRM_TI_TFP410) +=3D ti-tfp410.o >>>> +obj-$(CONFIG_DRM_TI_TMDS181) +=3D ti-tmds181.o >>>> obj-$(CONFIG_DRM_TI_TPD12S015) +=3D ti-tpd12s015.o >>>> obj-$(CONFIG_DRM_NWL_MIPI_DSI) +=3D nwl-dsi.o >>>> obj-$(CONFIG_DRM_ITE_IT66121) +=3D ite-it66121.o >>>> diff --git a/drivers/gpu/drm/bridge/ti-tmds181.c b/drivers/gpu/drm/bri= dge/ti-tmds181.c >>>> new file mode 100644 >>>> index 000000000000..34cbdb066820 >>>> --- /dev/null >>>> +++ b/drivers/gpu/drm/bridge/ti-tmds181.c >>>> @@ -0,0 +1,561 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> +/* >>>> + * TI tmds181 and sn65dp159 HDMI redriver and retimer chips >>>> + * >>>> + * Copyright (C) 2018 - 2025 Topic Embedded Products >>>> + * >>>> + * based on code >>>> + * Copyright (C) 2007 Hans Verkuil >>>> + * Copyright (C) 2016, 2017 Leon Woestenberg >>>> + */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +MODULE_DESCRIPTION("I2C device driver for DP159 and TMDS181 redriver/= retimer"); >>>> +MODULE_AUTHOR("Mike Looijmans"); >>>> +MODULE_LICENSE("GPL"); >>>> + >>>> +#define TMDS181_REG_ID 0 >>>> +#define TMDS181_REG_REV 0x8 >>>> +#define TMDS181_REG_CTRL9 0x9 >>>> +/* Registers A and B have a volatile bit, but we don't use it, so cac= he is ok */ >>>> +#define TMDS181_REG_CTRLA 0xA >>>> +#define TMDS181_REG_CTRLB 0xB >>>> +#define TMDS181_REG_CTRLC 0xC >>>> +#define TMDS181_REG_EQUALIZER 0xD >>>> +#define TMDS181_REG_EYESCAN 0xE >>>> + >>>> +#define TMDS181_CTRL9_SIG_EN BIT(4) >>>> +#define TMDS181_CTRL9_PD_EN BIT(3) >>>> +#define TMDS181_CTRL9_HPD_AUTO_PWRDWN_DISABLE BIT(2) >>>> +#define TMDS181_CTRL9_I2C_DR_CTL GENMASK(1, 0) >>>> + >>>> +#define TMDS181_CTRLA_MODE_SINK BIT(7) >>>> +#define TMDS181_CTRLA_HPDSNK_GATE_EN BIT(6) >>>> +#define TMDS181_CTRLA_EQ_ADA_EN BIT(5) >>>> +#define TMDS181_CTRLA_EQ_EN BIT(4) >>>> +#define TMDS181_CTRLA_AUX_BRG_EN BIT(3) >>>> +#define TMDS181_CTRLA_APPLY BIT(2) >>>> +#define TMDS181_CTRLA_DEV_FUNC_MODE GENMASK(1, 0) >>>> + >>>> +#define TMDS181_CTRLB_SLEW_CTL GENMASK(7, 6) >>>> +#define TMDS181_CTRLB_HDMI_SEL_DVI BIT(5) >>>> +#define TMDS181_CTRLB_TX_TERM_CTL GENMASK(4, 3) >>>> +#define TMDS181_CTRLB_DDC_DR_SEL BIT(2) >>>> +#define TMDS181_CTRLB_TMDS_CLOCK_RATIO_STATUS BIT(1) >>>> +#define TMDS181_CTRLB_DDC_TRAIN_SET BIT(0) >>>> + >>>> +#define TMDS181_CTRLB_TX_TERM_150_300_OHMS 1 >>>> +#define TMDS181_CTRLB_TX_TERM_75_150_OHMS 3 >>>> + >>>> +#define TMDS181_CTRLC_VSWING_DATA GENMASK(7, 5) >>>> +#define TMDS181_CTRLC_VSWING_CLK GENMASK(4, 2) >>>> +#define TMDS181_CTRLC_HDMI_TWPST1 GENMASK(1, 0) >>>> + >>>> +#define TMDS181_EQ_DATA_LANE GENMASK(5, 3) >>>> +#define TMDS181_EQ_CLOCK_LANE GENMASK(2, 1) >>>> +#define TMDS181_EQ_DIS_HDMI2_SWG BIT(0) >>>> + >>>> +/* Above this data rate HDMI2 standards apply (TX termination) */ >>>> +#define HDMI2_PIXEL_RATE_KHZ 340000 >>>> + >>>> +enum tmds181_chip { >>>> + tmds181, >>>> + dp159, >>>> +}; >>>> + >>>> +struct tmds181_data { >>>> + struct i2c_client *client; >>>> + struct regmap *regmap; >>>> + struct drm_bridge *next_bridge; >>>> + struct drm_bridge bridge; >>>> + u32 retimer_threshold_khz; >>>> + enum tmds181_chip chip; >>>> +}; >>>> + >>>> +static inline struct tmds181_data * >>>> +drm_bridge_to_tmds181_data(struct drm_bridge *bridge) >>>> +{ >>>> + return container_of(bridge, struct tmds181_data, bridge); >>>> +} >>>> + >>>> +/* Set "apply" bit in control register after making changes */ >>>> +static int tmds181_apply_changes(struct tmds181_data *data) >>>> +{ >>>> + return regmap_write_bits(data->regmap, TMDS181_REG_CTRLA, >>>> + TMDS181_CTRLA_APPLY, TMDS181_CTRLA_APPLY); >>>> +} >>>> + >>>> +static int tmds181_attach(struct drm_bridge *bridge, >>>> + enum drm_bridge_attach_flags flags) >>>> +{ >>>> + struct tmds181_data *data =3D drm_bridge_to_tmds181_data(bridge); >>>> + >>>> + return drm_bridge_attach(bridge->encoder, data->next_bridge, bridge, >>>> + flags); >>>> +} >>>> + >>>> +static enum drm_mode_status >>>> +tmds181_mode_valid(struct drm_bridge *bridge, const struct drm_displa= y_info *info, >>>> + const struct drm_display_mode *mode) >>>> +{ >>>> + /* Clock limits: clk between 25 and 350 MHz, clk is 1/10 of bit cloc= k */ >>>> + if (mode->clock < 25000) >>>> + return MODE_CLOCK_LOW; >>> I'm a bit confused by your comment here. Why do we care about the bit c= lock here? >> Purpose here is to filter out modes that certainly won't work. For examp= le, >> a standard 640x480 mode would have a 24MHz clock, which this chip doesn'= t >> support according to the datasheet. > Sure, but you're talking about the pixel clock here, not the bit clock. > So I'm still not sure why you need to mention it in the comment. > >>>> + /* The actual HDMI clock (if provided) cannot exceed 350MHz */ >>>> + if (mode->crtc_clock > 350000) >>>> + return MODE_CLOCK_HIGH; >>> And what do you call the "actual HDMI clock" and why wouldn't it be pro= vided? >> The clock signal on the HDMI cable. > That's not mode->clock or mode->crtc_clock then. The datasheets mention > that it can go from 0.25 to 6 Gbps. That's the TMDS char rate, which is > calculated using drm_hdmi_compute_mode_clock(). Added that, but it requires me to provide the bit depth and format,=20 which this bridge doesn't know. I can at least assume 8 bit and=20 HDMI_COLORSPACE_RGB as a "worst case" check for the upper limit, as=20 those are certain to fail. Fortunately the chip doesn't really care what's being transmitted, so=20 not knowing the HDMI format is no big issue. Users can always lower the=20 retimer threshold if their hardware does need it, which in the worst=20 case would lead to the chip consuming more power than needed (but likely=20 still less than without this driver). > >> Again, aim is to block modes that certainly won't work. >> >> While developing the driver (and logging lots) the crtc_clock was >> often just "0". >> >> This is still tricky though. What if we'd have a DSI-to-HDMI bridge in >> between this and the crtc, and outputting a 4k display mode? The >> DSI-to-HDMI bridge output clock (to the retimer) won't match the CRTC >> clock, nor would it match the pixel clock (using 1/40 clock rate). > It's not tricky, really. DRM internals only ever talks in pixel clock > rates, ie assuming a pixel gets sent out for each clock cycle. > > It will not be the case if the buses are somewhat-serial for example, > but it allows each bus driver to derive its own internal clock from the > pixel clock rate and its parameters. > > So your example works just fine, because on the DSI bus and on the HDMI > bus, you'd still get the same pixel clock rate. Indeed. > > Maxime --=20 Mike Looijmans System Expert TOPIC Embedded Products B.V. Materiaalweg 4, 5681 RJ Best The Netherlands T: +31 (0) 499 33 69 69 E: mike.looijmans@topic.nl W: www.topic.nl