From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m49231.qiye.163.com (mail-m49231.qiye.163.com [45.254.49.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F85A372B3A; Thu, 5 Mar 2026 08:49:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.231 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772700551; cv=none; b=SyftYW7gVcDSeFECwaxJmAC/hsM59Jzrxd7FPpiOA0EYNfVxo7t1VSHKRZTYNAp7pWtI2LkiaVxfQ2ZvNXaPZVq/NRllpZLTeUg65i6JraUDcnLMBbCevfdAf9W5fmu9RP8ljSGvWCEPCKIq5yZpBaqUS+vltKdrsirWSDlTesY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772700551; c=relaxed/simple; bh=pV+Iro7JyZt27/lvK3Fuib8o4AkilNOU9E0DTzmEJME=; h=Cc:Subject:To:References:From:Message-ID:Date:MIME-Version: In-Reply-To:Content-Type; b=d+9CgWqQB5+oP6EqKZXa9yywlSoePXPPSTvuorZhs8DjctNjn5B3NvnkWMjCvFaP7Uxy+Ibtn0lKWZlOQagFasDYHF2mvLFz/o9e5QpbZm4hbVWA2wNojL1hrk7UbEcuinm9J6Qayshs6BFYi7+CD2aqvjwLQX99f/kgepmpAWM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=EphQEB5a; arc=none smtp.client-ip=45.254.49.231 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="EphQEB5a" Received: from [172.16.12.14] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 35d3fe335; Thu, 5 Mar 2026 13:19:47 +0800 (GMT+08:00) Cc: shawn.lin@rock-chips.com, FUKAUMI Naoki , Hsun Lai , Jonas Karlman , Chaoyi Chen , John Clark , Michael Opdenacker , Quentin Schulz , Andrew Lunn , Alexey Charkov , Peter Robinson , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V2 3/3] arm64: dts: rockchip: Add Orange Pi 5 Pro board support To: dennis@ausil.us, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner References: <20260304025521.210377-1-dennis@ausil.us> <20260304025521.210377-4-dennis@ausil.us> From: Shawn Lin Message-ID: <24a7ae9d-48dc-8e9d-cead-fcfc3d1002fe@rock-chips.com> Date: Thu, 5 Mar 2026 13:19:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20260304025521.210377-4-dennis@ausil.us> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9cbc70144c09cckunm12c3cf4a12bb98e X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGR5KGlZPSh1LTU5OGUJIQhpWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=EphQEB5a5lXZilV6aoKge9NyalR0WZ+gIHyn5srrBIVwptXDzJqJyGm1/Xzi4ZolYQk0j0Br1mRv1RhdRK2b5gfoveBNhGEd6TWsXhyu8kaThH0EN/L4QuqLj0ZdbRntCwPmERBibCr8wDEiOOY+UwpNcDvY1P81S884eo78n9E=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=sLvwy6b/0z6rQLRM6bncv48l7DnkNMBLAlOIpSaLiMg=; h=date:mime-version:subject:message-id:from; 在 2026/03/04 星期三 10:55, dennis@ausil.us 写道: > From: Dennis Gilmore > > Add device tree for the Xunlong Orange Pi 5 Pro (RK3588S). The Pro > differs from the base Orange Pi 5 in the following ways: > > - No SPI NOR flash; eMMC module slot instead, you can optionally solder > a SPI NOR fin place and turn off the eMMC > - PCIe-attached NIC (pcie2x1l1) replaces the GMAC1 ethernet > - PCIe NVMe slot (pcie2x1l2) > - AP6256 WiFi (BCM43456) via SDIO with mmc-pwrseq > - BCM4345C5 Bluetooth via uart9 with full RTS/CTS > - Two-colour (blue/green) GPIO LED using modern color/function binding > - audio is wired up differently > > Vendors description and links to schematics available: > http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-Pro.html > > Signed-off-by: Dennis Gilmore > --- > arch/arm64/boot/dts/rockchip/Makefile | 1 + > .../dts/rockchip/rk3588s-orangepi-5-pro.dts | 376 ++++++++++++++++++ > 2 files changed, 377 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > index 4d384f153c13..c99dca2ae9e7 100644 > --- a/arch/arm64/boot/dts/rockchip/Makefile > +++ b/arch/arm64/boot/dts/rockchip/Makefile > @@ -214,6 +214,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5-pro.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-cm5-base.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-roc-pc.dtb > diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts > new file mode 100644 > index 000000000000..d656328c906d > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts > @@ -0,0 +1,376 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + > +/dts-v1/; > + > +#include "rk3588s-orangepi-5.dtsi" > + > +/ { > + model = "Xunlong Orange Pi 5 Pro"; > + compatible = "xunlong,orangepi-5-pro", "rockchip,rk3588s"; > + > + aliases { > + /delete-property/ ethernet0; > + mmc0 = &sdhci; > + mmc1 = &sdmmc; > + mmc2 = &sdio; > + }; > + > + /* Pro uses gpio-leds instead; pwm0 LED is not wired up */ > + /delete-node/ pwm-leds; > + > + /* > + * Pro uses i2s2 (i2s2m1 mux) for audio, not i2s1. Recreate the sound > + * card node pointing at i2s2_2ch instead. > + */ > + /delete-node/ analog-sound; > + > + analog-sound { > + compatible = "simple-audio-card"; > + pinctrl-names = "default"; > + pinctrl-0 = <&hp_detect>; > + simple-audio-card,bitclock-master = <&masterdai>; > + simple-audio-card,format = "i2s"; > + simple-audio-card,frame-master = <&masterdai>; > + simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; > + simple-audio-card,mclk-fs = <256>; > + simple-audio-card,name = "rockchip,es8388"; > + simple-audio-card,routing = > + "Headphones", "LOUT1", > + "Headphones", "ROUT1", > + "LINPUT1", "Microphone Jack", > + "RINPUT1", "Microphone Jack", > + "LINPUT2", "Onboard Microphone", > + "RINPUT2", "Onboard Microphone"; > + simple-audio-card,widgets = > + "Microphone", "Microphone Jack", > + "Microphone", "Onboard Microphone", > + "Headphone", "Headphones"; > + > + simple-audio-card,cpu { > + sound-dai = <&i2s2_2ch>; > + }; > + > + masterdai: simple-audio-card,codec { > + sound-dai = <&es8388>; > + system-clock-frequency = <12288000>; > + }; > + }; > + > + fan: pwm-fan { > + compatible = "pwm-fan"; > + #cooling-cells = <2>; > + cooling-levels = <0 50 100 150 200 255>; > + fan-supply = <&vcc5v0_sys>; > + pwms = <&pwm2 0 20000000 0>; > + }; > + > + gpio-leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&leds_rgb>; > + > + blue-led { > + color = ; > + function = LED_FUNCTION_STATUS; > + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "heartbeat"; > + }; > + > + green-led { > + color = ; > + function = LED_FUNCTION_ACTIVITY; > + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "mmc0"; > + }; > + }; > + > + vcc5v0_otg: regulator-vcc5v0-otg { > + compatible = "regulator-fixed"; > + enable-active-high; > + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; > + pinctrl-names = "default"; > + pinctrl-0 = <&vcc5v0_otg_en>; > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <5000000>; > + regulator-name = "vcc5v0_otg"; > + vin-supply = <&vcc5v0_sys>; > + }; > + > + sdio_pwrseq: sdio-pwrseq { > + compatible = "mmc-pwrseq-simple"; > + clocks = <&hym8563>; > + clock-names = "ext_clock"; > + post-power-on-delay-ms = <200>; > + reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_LOW>; > + }; > + > + vcc3v3_pcie20: regulator-vcc3v3-pcie20 { > + compatible = "regulator-fixed"; > + enable-active-high; > + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + regulator-name = "vcc3v3_pcie20"; > + startup-delay-us = <50000>; > + vin-supply = <&vcc5v0_sys>; > + }; > + > + vcc3v3_pcie_eth: regulator-vcc3v3-pcie-eth { > + compatible = "regulator-fixed"; > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + regulator-name = "vcc3v3_pcie_eth"; > + vin-supply = <&vcc5v0_sys>; > + }; > +}; > + > +/* disable gmac1 as the pro has a PCIe attached NIC */ > +&gmac1 { > + status = "disabled"; > +}; > + > +/* 40-pin header pins 3/5 */ > +&i2c1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c1m4_xfer>; > + status = "okay"; > +}; > + > +/* > + * Pro routes audio codec via i2c3 (not i2c6) and i2s2m1 (not i2s1m0). > + * Delete the inherited es8388 node from i2c6 and redeclare it here. > + */ > +/delete-node/ &es8388; > + > +&i2c3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c3m0_xfer>; > + status = "okay"; > + > + es8388: audio-codec@11 { > + compatible = "everest,es8388", "everest,es8328"; > + reg = <0x11>; > + #sound-dai-cells = <0>; > + AVDD-supply = <&vcc_3v3_s0>; > + DVDD-supply = <&vcc_1v8_s0>; > + HPVDD-supply = <&vcc_3v3_s0>; > + PVDD-supply = <&vcc_3v3_s0>; > + assigned-clock-rates = <12288000>; > + assigned-clocks = <&cru I2S2_2CH_MCLKOUT>; > + clocks = <&cru I2S2_2CH_MCLKOUT>; > + }; > +}; > + > +/* 40-pin header pins 27/28 */ > +&i2c4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c4m3_xfer>; > + status = "okay"; > +}; > + > +/* > + * i2s1_8ch uses i2s1m0 which occupies GPIO4_PA0 (CLKREQ#) and GPIO4_PA1 > + * (WAKE#) needed for the NVMe M.2 slot. Disable it; audio is on i2s2_2ch. > + */ > +&i2s1_8ch { > + status = "disabled"; > +}; > + > +/* Audio codec on i2s2, m1 mux; add mclk pin to the base pinctrl */ > +&i2s2_2ch { > + pinctrl-0 = <&i2s2m1_lrck &i2s2m1_mclk &i2s2m1_sclk > + &i2s2m1_sdi &i2s2m1_sdo>; > + status = "okay"; > +}; > + > +&package_thermal { > + polling-delay = <1000>; > + > + cooling-maps { > + map0 { > + trip = <&package_fan0>; > + cooling-device = <&fan THERMAL_NO_LIMIT 1>; > + }; > + > + map1 { > + trip = <&package_fan1>; > + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; > + }; > + }; > + > + trips { > + package_fan0: package-fan0 { > + hysteresis = <2000>; > + temperature = <55000>; > + type = "active"; > + }; > + > + package_fan1: package-fan1 { > + hysteresis = <2000>; > + temperature = <65000>; > + type = "active"; > + }; > + }; > +}; > + > +/* NVMe */ > +&pcie2x1l1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie30x1m1_1_clkreqn &pcie30x1m1_1_waken>; > + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; > + supports-clkreq; > + vpcie3v3-supply = <&vcc3v3_pcie_eth>; I don't get this. NVMe M.2 slot uses power for eth? > + status = "okay"; > +}; > + > +/* NIC */ > +&pcie2x1l2 { > + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; > + vpcie3v3-supply = <&vcc3v3_pcie20>; The same question as above. > + status = "okay"; > +}; > + > +&pinctrl { > + bluetooth { > + bt_wake_gpio: bt-wake-pin { > + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + > + bt_wake_host_irq: bt-wake-host-irq { > + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; > + }; > + }; > + > + gpio-leds { > + leds_rgb: leds-rgb { > + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, > + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > + > + usb { > + vcc5v0_otg_en: vcc5v0-otg-en { > + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > + > + wlan { > + wifi_host_wake_irq: wifi-host-wake-irq { > + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; > + }; > + }; > +}; > + > +/* pwm0 pin conflicts with i2c4 pin 27 Pro */ > +&pwm0 { > + status = "disabled"; > +}; > + > +&pwm2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm2m1_pins>; > + status = "okay"; > +}; > + > +&sdhci { > + status = "okay"; > +}; > + > +&sdio { > + #address-cells = <1>; > + #size-cells = <0>; > + bus-width = <4>; > + cap-sd-highspeed; > + cap-sdio-irq; > + disable-wp; Please remove disable-wp for SDIO device. > + keep-power-in-suspend; > + max-frequency = <150000000>; > + mmc-pwrseq = <&sdio_pwrseq>; > + no-mmc; > + no-sd; > + non-removable; > + sd-uhs-sdr104; > + status = "okay"; > + > + ap6256: wifi@1 { > + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; > + reg = <1>; > + interrupt-names = "host-wake"; > + interrupt-parent = <&gpio0>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&wifi_host_wake_irq>; > + }; > +}; > + > +&uart9 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn &uart9m2_rtsn>; > + uart-has-rtscts; > + status = "okay"; > + > + bluetooth { > + compatible = "brcm,bcm4345c5"; > + clocks = <&hym8563>; > + clock-names = "lpo"; > + device-wakeup-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; > + interrupt-names = "host-wakeup"; > + interrupt-parent = <&gpio0>; > + interrupts = ; > + max-speed = <1500000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&bt_wake_host_irq &bt_wake_gpio>; > + shutdown-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; > + vbat-supply = <&vcc_3v3_s3>; > + vddio-supply = <&vcc_1v8_s3>; > + }; > +}; > + > +/* USB2 OTG PHY for usb_host0_xhci; phy-supply enables VBUS to USB3 Type-A port */ > +&u2phy0_otg { > + phy-supply = <&vcc5v0_otg>; > +}; > + > +/* Pro has no FUSB302; the USB-C port is power delivery only */ > +/delete-node/ &usbc0; > + > +/* > + * The Pro's USB-C port is power delivery only: no FUSB302, no data lines, > + * no alt-mode switching. The parent DTSI enables usbdp_phy0 (status = "okay") > + * and adds FUSB302 alt-mode/orientation properties; delete those here. > + * > + * dp-lane-mux = <0 1>: PHY lanes 0/1 are DP (physically routed to the > + * LT8711UXD DP→HDMI2 bridge), lanes 2/3 are USB3 SuperSpeed (physically > + * routed to the USB3 Type-A port P3). Without this property the driver > + * defaults to USB-only mode and places USB3 on lanes 0/1, which do not > + * reach the Type-A connector and makes the USB3 port non-functional. > + */ > +&usbdp_phy0 { > + rockchip,dp-lane-mux = <0 1>; > + /delete-property/ mode-switch; > + /delete-property/ orientation-switch; > + /delete-property/ sbu1-dc-gpios; > + /delete-property/ sbu2-dc-gpios; > + /delete-node/ port; > +}; > + > +/* USB3 Type-A port*/ > +&usb_host0_xhci { > + dr_mode = "host"; > + /delete-property/ usb-role-switch; > + status = "okay"; > + /delete-node/ port; > +}; > + > +/* > + * combphy2_psu is shared between usb_host2_xhci (USB3) and pcie2x1l1 (PCIe). > + * Disable USB3 so the PHY can be used for the NVMe M.2 slot. > + */ > +&usb_host2_xhci { > + status = "disabled"; > +}; >