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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id c130sm29316546wmf.47.2019.05.13.02.58.43 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 13 May 2019 02:58:44 -0700 (PDT) Message-ID: <24b8cd2eb2879378ca0cac6ddfd9c5cae68699bc.camel@baylibre.com> Subject: Re: [PATCH 0/3] mmc: meson-gx: add ddr-access-quirk support From: Jerome Brunet To: Neil Armstrong , ulf.hansson@linaro.org, khilman@baylibre.com Cc: baylibre-upstreaming@groups.io, linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Mon, 13 May 2019 11:58:43 +0200 In-Reply-To: <20190513091548.16674-1-narmstrong@baylibre.com> References: <20190513091548.16674-1-narmstrong@baylibre.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5 (3.30.5-1.fc29) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2019-05-13 at 11:15 +0200, Neil Armstrong wrote: > On the Amlogic G12A SoC family, (only) the SDIO controller fails to access > the data from DDR, leading to a broken controller. > > Add the amlogic,ddr-access-quirk property so signal this particular > controller has this bug and needs a quirk to work properly. > > But each MMC controller has 1,5KiB of SRAM after the registers, that can > be used as bounce buffer to avoid direct DDR access from the integrated > DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized). > > The quirk is to disable the chained descriptor for this controller, and > use this SRAM memory zone as buffer for the bounce buffer fallback mode. > > The performance hit hasn't been evaluated, but the fix has been tested > using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave > 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed > at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock. These numbers looks to be limited by the MMC bandwidth of the related modes. So, if the SRAM quirk introduce a penalty for the controller, it does not appear to be a limiting factor, AFAICT. > > Neil Armstrong (3): > dt-bindings: mmc: meson-gx: add ddr-access-quirk property > mmc: meson-gx: add ddr-access-quirk > arm64: dts: meson-g12a: add ddr-access-quirk property to SDIO > controller > > .../bindings/mmc/amlogic,meson-gx.txt | 4 ++ > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + > drivers/mmc/host/meson-gx-mmc.c | 65 +++++++++++++++---- > 3 files changed, 57 insertions(+), 13 deletions(-) >