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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231e069c592sm755765ad.100.2025.05.15.17.39.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 17:39:08 -0700 (PDT) Message-ID: <24e419da-71f8-4b0d-9416-0fe4c63eed0f@oss.qualcomm.com> Date: Thu, 15 May 2025 17:39:06 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] drm/msm/dpu: Check mode against PINGPONG or DSC max width To: Dmitry Baryshkov Cc: Rob Clark , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Abhinav Kumar , Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com> <20250514-max-mixer-width-v1-3-c8ba0d9bb858@oss.qualcomm.com> Content-Language: en-US From: Jessica Zhang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: GyPFquNOCqpoMetzfouwF9bFR03-q2AO X-Authority-Analysis: v=2.4 cv=D8dHKuRj c=1 sm=1 tr=0 ts=6826892d cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=lZyNh1K7jJI6hNXvg3QA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDAwMyBTYWx0ZWRfX9YzOm8yv52it mMq+K9D5hhBUbdDWmE5Co+FCZ9gh3pmWa5Uoz/vxuv39G6kct/tTAheoXxnMJok/PVyR74wgCf+ Uq5hEYdu9dQDuLM+LF73aCvdnfMNylfsiVOQBOOX/oxHHVVQLhn5st9vKSmer492w1uBGkBp6Pp kRROcTzFwJt+7PHh2vyIqxnR3dicOLnbvIfxzP0GsFHavq9sbVCj42ENvkFCWk8cwpvlhBJMTOv uHymsWXY97dhEsryGONtR+GP63byZBLTg8UhFMp/otU++lRWaaF7zzjKv+M7uWGAPRXPYaDgyq4 HGR+XDjhrYCcCpEyBE2l4tOj9ASPapsGYYzkGQRtDTtQcFFonQC7PUVMAzxiKLWQM5VhSL4NQkY Gb70W9sznOAoSU2QlqrvJsf3LnwVM1lnDMgugQIuIMYpFW+pAXhIVkOyvpUmMpQ64ONOcZlS X-Proofpoint-GUID: GyPFquNOCqpoMetzfouwF9bFR03-q2AO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_11,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160003 On 5/14/2025 5:28 PM, Dmitry Baryshkov wrote: > On Wed, May 14, 2025 at 04:52:31PM -0700, Jessica Zhang wrote: >> Validate requested mode and topology based on the PINGPONG or DSC encoder >> max width. In addition, drop MAX_HDISPLAY_SPLIT and base LM reservation >> off of PINGPONG or DSC encoder max width > > Separate commit for num_lm, please. Hi Dmitry, Ack. > >> >> As noted in the patch, while DPU 8.x+ supports a max linewidth of 8960 >> for PINGPONG_0, there is some additional logic that needs to be added to >> the resource manager to specifically try and reserve PINGPONG_0 for >> modes that are greater than 5k. >> >> Since this is out of the scope of this series, add a helper that will >> get the overall minimum PINGPONG max linewidth for a given chipset. >> >> Signed-off-by: Jessica Zhang >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 46 +++++++++++++++++++++++++++----- >> 1 file changed, 39 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> index 0714936d8835..6131d071b051 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> @@ -723,6 +723,31 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc) >> _dpu_crtc_complete_flip(crtc); >> } >> >> +static int msm_display_get_max_pingpong_width(struct dpu_kms *dpu_kms) >> +{ >> + const struct dpu_pingpong_cfg *pingpong; >> + u32 max_pingpong_width = dpu_kms->catalog->pingpong[0].max_linewidth; >> + >> + /* >> + * Find the smallest overall PINGPONG max_linewidth in the catalog since >> + * max_linewidth can differ between PINGPONGs even within the same >> + * chipset. >> + * >> + * Note: While, for DPU 8.x+, PINGPONG_0 can technically support up to >> + * 8k resolutions, this requires reworking the RM to try to reserve >> + * PINGPONG_0 for modes greater than 5k. >> + * >> + * Once this additional logic is implemented, we can drop this helper >> + * and use the reserved PINGPONG's max_linewidth >> + */ >> + for (int i = 1; i < dpu_kms->catalog->pingpong_count; i++) { >> + pingpong = &dpu_kms->catalog->pingpong[i]; >> + max_pingpong_width = min(max_pingpong_width, pingpong->max_linewidth); >> + } > > Since we are skipping PINGPONG_0, wouldn't it be enough to return > max_linewidth of PP_1 ? I don't think we're skipping PINGPONG_0 here since `u32 max_pingpong_width = dpu_kms->catalog->pingpong[0].max_linewidth;` at the top of the function. > > I think, it would be easier to follow .max_dsc_encoder_width and store > .max_pingpong_linewidth in dpu_caps (and later add special > .max_pp0_linewidth). Ack. I think my only concern for this is that max_pp0_linewidth won't be set for all chipsets. But if you're fine with that I'll go ahead and make this change. Thanks, Jessica Zhang > >> + >> + return max_pingpong_width; >> +} >> + >> static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc, >> struct drm_crtc_state *state) >> { >