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From: Robin Murphy <robin.murphy@arm.com>
To: Jim Quinlan <jim2101024@gmail.com>,
	Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Cc: Florian Fainelli <f.fainelli@gmail.com>,
	maz@kernel.org, Phil Elwell <phil@raspberrypi.org>,
	linux-kernel@vger.kernel.org,
	Jeremy Linton <jeremy.linton@arm.com>,
	Eric Anholt <eric@anholt.net>,
	mbrugger@suse.com,
	bcm-kernel-feedback-list <bcm-kernel-feedback-list@broadcom.com>,
	Stefan Wahren <wahrenst@gmx.net>,
	Jim Quinlan <james.quinlan@broadcom.com>,
	linux-pci <linux-pci@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Andrew Murray <andrew.murray@arm.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>,
	linux-rpi-kernel@lists.infradead.org
Subject: Re: [PATCH v2 4/6] PCI: brcmstb: add Broadcom STB PCIe host controller driver
Date: Fri, 22 Nov 2019 14:59:06 +0000	[thread overview]
Message-ID: <24e5302a-51c6-df39-5381-a790752f261d@arm.com> (raw)
In-Reply-To: <CANCKTBuoSkmAiY4yUuNpT-GwhS7LJv79L910UvcrPgPpMz=YGg@mail.gmail.com>

On 21/11/2019 9:07 pm, Jim Quinlan wrote:
[...]
>> As for [...]_NUM_MASK_BITS I'm looking for a smart/generic way to calculate it
>> from the actual mask. No luck so far. If not, I think I'll simply leave it as
>> is for now.

HWEIGHT()?

>>>> FYI, What's happening here is that we have to save the CPU address range
>>>> (which
>>>> is already shifted right 20 positions) in two parts, the lower 12 bits go
>>>> into
>>>> PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT while the higher 8 bits go into
>>>> PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI or
>>>> PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI.
>>>
>>> The hardware spec require bits 31:20 of the address, and the high registers
>>> require 39:32 right?
>>
>> Yes, that's it.
>>
>>> (Apologies, the indirection by the WR_FLD_** macros easily confuses me. These
>>> type of macros are helpful, or rather would be if the whole kernel used them.
>>> I think they can add confusion when each driver has its own set of similar
>>> macros. This is why its *really* helpful to use any existing macros in the
>>> kernel - and only invent new ones if needed).
>>
>> I agree it's pretty confusing, I think v3, using bitfield.h as much as
>> possible, looks substantially more welcoming.
> 
> The reason we use custom macros is because we'd like to keep the
> register names the same as the HW declares and our internal tools
> support.  As you may have noticed, our register names are unusually
> long and it is hard to fit a simple read or write field assignment
> within 80 columns w/o using custom macros tailored to our register
> names' format.
> 
> Perhaps Nicolas can pull a rabbit out of a hat and use Linux macros
> while keeping our long register names, but if he has to use his own
> shorter register names it will become harder for Broadcom developers
> to debug this driver.

Regardless of the length of the names, the standard bitfield helpers can 
still make things easier to reason about - in this particular case I 
think you could lose some boilerplate and indirection with essentially 
no change to the readability you're concerned for - compare:

#define REG_NAME ...
#define REG_NAME_FIELD_NAME_MASK ...
#define REG_NAME_FIELD_NAME_SHIFT ...

	val = RD_FIELD(base, REG_NAME,
		       FIELD_NAME);

vs.

#define REG_NAME ...
#define   FIELD_NAME ...

	reg = bcm_readl(base + REG_NAME);
	val = FIELD_GET(FIELD_NAME, reg);

Robin.

  reply	other threads:[~2019-11-22 14:59 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-12 15:59 [PATCH v2 0/6] Raspberry Pi 4 PCIe support Nicolas Saenz Julienne
2019-11-12 15:59 ` [PATCH v2 1/6] linux/log2.h: Add roundup/rounddown_pow_two64() family of functions Nicolas Saenz Julienne
2019-11-19 11:13   ` Andrew Murray
2019-11-19 11:30     ` Nicolas Saenz Julienne
2019-11-19 12:43       ` Nicolas Saenz Julienne
2019-11-19 16:28         ` Andrew Murray
2019-11-19 16:55           ` Jason Gunthorpe
2019-11-19 17:00             ` Andrew Murray
2019-11-12 15:59 ` [PATCH v2 2/6] dt-bindings: PCI: Add bindings for brcmstb's PCIe device Nicolas Saenz Julienne
2019-11-18 21:23   ` Rob Herring
2019-11-19  9:35     ` Nicolas Saenz Julienne
2019-11-19 11:17   ` Andrew Murray
2019-11-19 11:28     ` Nicolas Saenz Julienne
2019-11-12 15:59 ` [PATCH v2 3/6] ARM: dts: bcm2711: Enable PCIe controller Nicolas Saenz Julienne
2019-11-12 15:59 ` [PATCH v2 4/6] PCI: brcmstb: add Broadcom STB PCIe host controller driver Nicolas Saenz Julienne
2019-11-19 16:25   ` Andrew Murray
2019-11-19 18:20     ` Jeremy Linton
2019-11-20 20:24       ` Nicolas Saenz Julienne
2019-11-19 18:34     ` Florian Fainelli
2019-11-21 12:16       ` Andrew Murray
2019-11-20 19:53     ` Nicolas Saenz Julienne
2019-11-21 12:03       ` Andrew Murray
2019-11-21 12:59         ` Nicolas Saenz Julienne
2019-11-21 15:44           ` Andrew Murray
2019-11-21 21:07           ` Jim Quinlan
2019-11-22 14:59             ` Robin Murphy [this message]
2019-11-21 13:26         ` Nicolas Saenz Julienne
2019-11-21 15:46           ` Andrew Murray
2019-11-12 15:59 ` [PATCH v2 5/6] PCI: brcmstb: add MSI capability Nicolas Saenz Julienne
2019-11-13 13:49   ` Marc Zyngier
2019-11-21 15:38   ` Andrew Murray
2019-11-21 17:19     ` Nicolas Saenz Julienne
2019-11-12 15:59 ` [PATCH v2 6/6] MAINTAINERS: Add brcmstb PCIe controller Nicolas Saenz Julienne
2019-11-19 11:18 ` [PATCH v2 0/6] Raspberry Pi 4 PCIe support Andrew Murray
2019-11-19 11:49   ` Nicolas Saenz Julienne
2019-11-21 12:18     ` Andrew Murray

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