From: "Clément Léger" <cleger@rivosinc.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: Re: [PATCH 2/6] riscv: request misaligned exception delegation from SBI
Date: Fri, 17 Jan 2025 16:09:27 +0100 [thread overview]
Message-ID: <24f9b863-9b88-4a58-a7a0-b562f6be56ad@rivosinc.com> (raw)
In-Reply-To: <fca2a328-f2c4-4df3-9086-06b8a12b8da4@sifive.com>
On 11/01/2025 00:35, Samuel Holland wrote:
> Hi Clément,
>
> On 2025-01-06 9:48 AM, Clément Léger wrote:
>> Now that the kernel can handle misaligned accesses in S-mode, request
>> misaligned access exception delegation from SBI. This uses the FWFT SBI
>> extension defined in SBI version 3.0.
>>
>> Signed-off-by: Clément Léger <cleger@rivosinc.com>
>> ---
>> arch/riscv/include/asm/cpufeature.h | 1 +
>> arch/riscv/kernel/traps_misaligned.c | 59 ++++++++++++++++++++++
>> arch/riscv/kernel/unaligned_access_speed.c | 2 +
>> 3 files changed, 62 insertions(+)
>>
>> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
>> index 4bd054c54c21..cd406fe37df8 100644
>> --- a/arch/riscv/include/asm/cpufeature.h
>> +++ b/arch/riscv/include/asm/cpufeature.h
>> @@ -62,6 +62,7 @@ void __init riscv_user_isa_enable(void);
>> _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate)
>>
>> bool check_unaligned_access_emulated_all_cpus(void);
>> +void unaligned_access_init(void);
>> #if defined(CONFIG_RISCV_SCALAR_MISALIGNED)
>> void check_unaligned_access_emulated(struct work_struct *work __always_unused);
>> void unaligned_emulation_finish(void);
>> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
>> index 7cc108aed74e..4aca600527e9 100644
>> --- a/arch/riscv/kernel/traps_misaligned.c
>> +++ b/arch/riscv/kernel/traps_misaligned.c
>> @@ -16,6 +16,7 @@
>> #include <asm/entry-common.h>
>> #include <asm/hwprobe.h>
>> #include <asm/cpufeature.h>
>> +#include <asm/sbi.h>
>> #include <asm/vector.h>
>>
>> #define INSN_MATCH_LB 0x3
>> @@ -689,3 +690,61 @@ bool check_unaligned_access_emulated_all_cpus(void)
>> return false;
>> }
>> #endif
>> +
>> +#ifdef CONFIG_RISCV_SBI
>> +
>> +struct misaligned_deleg_req {
>> + bool enable;
>> + int error;
>> +};
>> +
>> +static void
>> +cpu_unaligned_sbi_request_delegation(void *arg)
>> +{
>> + struct misaligned_deleg_req *req = arg;
>> + struct sbiret ret;
>> +
>> + ret = sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_SET,
>> + SBI_FWFT_MISALIGNED_EXC_DELEG, req->enable, 0, 0, 0, 0);
>> + if (ret.error)
>> + req->error = 1;
>> +}
>> +
>> +static void unaligned_sbi_request_delegation(void)
>> +{
>> + struct misaligned_deleg_req req = {true, 0};
>> +
>> + on_each_cpu(cpu_unaligned_sbi_request_delegation, &req, 1);
>> + if (!req.error) {
>> + pr_info("SBI misaligned access exception delegation ok\n");
>> + /*
>> + * Note that we don't have to take any specific action here, if
>> + * the delegation is successful, then
>> + * check_unaligned_access_emulated() will verify that indeed the
>> + * platform traps on misaligned accesses.
>> + */
>> + return;
>> + }
>> +
>> + /*
>> + * If at least delegation request failed on one hart, revert misaligned
>> + * delegation for all harts, if we don't do that, we'll panic at
>> + * misaligned delegation check time (see
>> + * check_unaligned_access_emulated()).
>> + */
>> + req.enable = false;
>> + req.error = 0;
>> + on_each_cpu(cpu_unaligned_sbi_request_delegation, &req, 1);
>> + if (req.error)
>> + panic("Failed to disable misaligned delegation for all CPUs\n");
>
> This logic doesn't handle the case where the delegation request failed on every
> CPU, so there's nothing to revert. This causes a panic in a KVM guest inside
> qemu-softmmu (the host kernel detects MISALIGNED_SCALAR_FAST, so
> unaligned_ctl_available() returns false, and all FWFT calls fail).
Hi Samuel,
Indeed, that's a problem and the revert is not really clean since it is
called on all CPUs (even tha rone that failed). I'll modify that to use
cpumasks and thus cleanly revert the misaligned delegation on CPUs that
actually succeeded only.
Thanks,
Clément
>
> Regards,
> Samuel
>
>> +
>> +}
>> +
>> +void unaligned_access_init(void)
>> +{
>> + if (sbi_probe_extension(SBI_EXT_FWFT) > 0)
>> + unaligned_sbi_request_delegation();
>> +}
>> +#else
>> +void unaligned_access_init(void) {}
>> +#endif
>> diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c
>> index 91f189cf1611..1e3166100837 100644
>> --- a/arch/riscv/kernel/unaligned_access_speed.c
>> +++ b/arch/riscv/kernel/unaligned_access_speed.c
>> @@ -403,6 +403,8 @@ static int check_unaligned_access_all_cpus(void)
>> {
>> bool all_cpus_emulated, all_cpus_vec_unsupported;
>>
>> + unaligned_access_init();
>> +
>> all_cpus_emulated = check_unaligned_access_emulated_all_cpus();
>> all_cpus_vec_unsupported = check_vector_unaligned_access_emulated_all_cpus();
>>
>
next prev parent reply other threads:[~2025-01-17 15:09 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-06 15:48 [PATCH 0/6] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-01-06 15:48 ` [PATCH 1/6] riscv: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-01-10 23:24 ` Samuel Holland
2025-01-06 15:48 ` [PATCH 2/6] riscv: request misaligned exception delegation from SBI Clément Léger
2025-01-07 3:28 ` Jesse T
2025-01-10 23:35 ` Samuel Holland
2025-01-17 15:09 ` Clément Léger [this message]
2025-01-06 15:48 ` [PATCH 3/6] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-01-10 23:42 ` Samuel Holland
2025-01-17 15:50 ` Clément Léger
2025-01-06 15:48 ` [PATCH 4/6] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-01-10 23:47 ` Samuel Holland
2025-01-06 15:48 ` [PATCH 5/6] riscv: export unaligned_ctl_available() as a GPL symbol Clément Léger
2025-01-07 3:34 ` Jesse T
2025-01-06 15:48 ` [PATCH 6/6] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-01-10 23:55 ` Samuel Holland
2025-01-17 16:05 ` Clément Léger
2025-01-17 16:31 ` Samuel Holland
2025-01-20 8:25 ` Clément Léger
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