From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752189AbbEGPSe (ORCPT ); Thu, 7 May 2015 11:18:34 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:62226 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751488AbbEGPSa (ORCPT ); Thu, 7 May 2015 11:18:30 -0400 From: Arnd Bergmann To: Mike Looijmans Cc: linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] arm/mm/dma-mapping.c: Add arm_coherent_dma_mmap Date: Thu, 07 May 2015 17:18:25 +0200 Message-ID: <2510023.oRzFOK8gGd@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <1431003257-7794-1-git-send-email-mike.looijmans@topic.nl> References: <1431003257-7794-1-git-send-email-mike.looijmans@topic.nl> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:T6DygikNZiwzbFvnC6rg0tTnVBZ0eIuL14W92xT8L1mqCqtwfGa n2aBy61wLY/LaBQjjkBIuGYqMk0eU5QqDmVsRyKtleamUEsNinfDKOGYpRtTlPAyC7+dsDA NpxP5cfSktBtgjq8cUx/Vejd2QRqAE31POqDD1B+ZTJaZAAWSyt9QHv09Y8xmq41XV0JhF9 ILLhOeD6p8xzBHYDKp6vg== X-UI-Out-Filterresults: notjunk:1; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 07 May 2015 14:54:17 Mike Looijmans wrote: > When dma-coherent transfers are enabled, the mmap call must > not change the pg_prot flags in the vma struct. > > Split the arm_dma_mmap into a common and specific parts, > and add a "arm_coherent_dma_mmap" implementation that does > not alter the page protection flags. > > Tested on a topic-miami board (Zynq) using the ACP port > to transfer data between FPGA and CPU using the Dyplo > framework. Without this patch, byte-wise access to mmapped > coherent DMA memory was about 20x slower because of the > memory being marked as non-cacheable, and transfer speeds > would not exceed 240MB/s. > > After this patch, the mapped memory is cacheable and the > transfer speed is again 600MB/s (limited by the FPGA) when > the data is in the L2 cache, while data integrity is being > maintained. > > The patch has no effect on non-coherent DMA. > > Signed-off-by: Mike Looijmans > Looks good to me Acked-by: Arnd Bergmann