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Tue, 21 Jul 2026 19:24:41 -0700 (PDT) X-Received: by 2002:a05:6a00:830c:b0:847:950b:b71a with SMTP id d2e1a72fcca58-84e15fb34f4mr1584963b3a.16.1784687081321; Tue, 21 Jul 2026 19:24:41 -0700 (PDT) Received: from [10.233.16.34] ([114.94.8.21]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84e17578345sm530778b3a.39.2026.07.21.19.24.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2026 19:24:40 -0700 (PDT) Message-ID: <2512aab8-fbde-4b95-8619-6c32d60ab500@oss.qualcomm.com> Date: Wed, 22 Jul 2026 10:24:35 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v15 4/8] phy: qcom-mipi-csi2: Parametrise the common status register offset To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati References: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> <20260720-kaanapali-camss-v15-4-c0b1c1167c5d@oss.qualcomm.com> Content-Language: en-US From: Hangxiang Ma In-Reply-To: <20260720-kaanapali-camss-v15-4-c0b1c1167c5d@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: eMHBR4fLYGwXv-0GKGtNgkYnzjltqhJC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIyMDAyMCBTYWx0ZWRfX4i9sgJRKpxbi +3h+VzVmksTmW8NNtF30YutG21dkXMlqZMZNMEzJZJRAszPLjM5uoq/iHq77vSLGO8xyuSp8giy 46A+0lkEhUBk/iiM1Z4dNd6rMeVVS/csyV/arzIWBZMuDyAkVz7hwLrnNNLdAXO1yudz/9NvtzL 2XaaYMUjFbbm5dgR3wVmZI3U99Vfcc5SJ8jlSYzcDAI+weBtZFxif59D6VDIWfvEmoGc37Upuxj Wj93Ir9AcvCRKdwGtwQexclgNMCwoB7achiIkAYCRLN5BqikguBCG7lF9n66+D11pD7gkgraPeF hbK+8rIoTKuc5uqG6+mqZ7iIt5ISGJul/CifwlIOtrsAWw1/Sxm8QL2gJMzqxXReMGD9OK5aet9 NqXQ9n1iMXaDRT9FhAsDMGmcDSMXcRj3aK+VwQAz0LLr8XXWmqHir25NMB+Zy46MEA0xmjNdqLQ vvz8eRDjRw6DQq3JS3A== X-Authority-Analysis: v=2.4 cv=e/o2j6p/ c=1 sm=1 tr=0 ts=6a6029ea cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=8VO9FOUX2GVN--3Z4zYA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: eMHBR4fLYGwXv-0GKGtNgkYnzjltqhJC X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIyMDAyMCBTYWx0ZWRfX8B9QDrk2dklq k4opWp5QduMxCa19UAPJ03ev0Xndiyfc1hOsunCPDgc8Ve5gm2IbqWbxA7lGSgw0Kk95gAsByPi cx9V4bRDyYB3qqk2BLHvsrLbkH2VpSw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-22_01,2026-07-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607220020 On 7/21/2026 12:50 PM, Hangxiang Ma wrote: > The CSI2 PHY common status registers are not at a fixed offset from the > common register block across SoCs: x1e80100 uses 0xb0 while other 3PH > v2.4.0 parts differ. > > Replace the hard-coded 0xb0 in CSIPHY_3PH_CMN_CSI_COMMON_STATUSn() with > a per-SoC common_status_offset field in struct mipi_csi2phy_device_regs, > initialising x1e80100 to 0xb0 so behaviour is unchanged. This is a > no-functional-change preparation for describing other SoC offsets. > > Signed-off-by: Hangxiang Ma > --- > drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 16 +++++++++++----- > drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + > 2 files changed, 12 insertions(+), 5 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c > index 966d79c98f9b..8cd331cfb4b3 100644 > --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c > +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c > @@ -19,7 +19,8 @@ > #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) > #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) > #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL10_IRQ_CLEAR_CMD BIT(0) > -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n)) > +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, common_status_offset, n) \ > + ((offset) + (common_status_offset) + 0x4 * (n)) > > #define CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(n) ((0x200 * (n)) + 0x24) > > @@ -176,19 +177,23 @@ static void phy_qcom_mipi_csi2_hw_version_read(struct mipi_csi2phy_device *csi2p > CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6)); > > tmp = readl_relaxed(csi2phy->base + > - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 12)); > + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, > + regs->common_status_offset, 12)); > csi2phy->hw_version = tmp; > > tmp = readl_relaxed(csi2phy->base + > - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 13)); > + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, > + regs->common_status_offset, 13)); > csi2phy->hw_version |= (tmp << 8) & 0xFF00; > > tmp = readl_relaxed(csi2phy->base + > - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 14)); > + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, > + regs->common_status_offset, 14)); > csi2phy->hw_version |= (tmp << 16) & 0xFF0000; > > tmp = readl_relaxed(csi2phy->base + > - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 15)); > + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, > + regs->common_status_offset, 15)); > csi2phy->hw_version |= (tmp << 24) & 0xFF000000; > > dev_dbg_once(csi2phy->dev, "CSIPHY 3PH HW Version = 0x%08x\n", csi2phy->hw_version); > @@ -375,6 +380,7 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { > .init_seq = lane_regs_x1e80100, > .lane_array_size = ARRAY_SIZE(lane_regs_x1e80100), > .common_regs_offset = 0x1000, > + .common_status_offset = 0xb0, > }, > .supply_names = (const char **)x1e_supplies, > .num_supplies = ARRAY_SIZE(x1e_supplies), > diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h > index 7e55ae007370..d6366f809e51 100644 > --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h > +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h > @@ -51,6 +51,7 @@ struct mipi_csi2phy_device_regs { > const struct mipi_csi2phy_lane_regs *init_seq; > const int lane_array_size; > const u32 common_regs_offset; > + const u32 common_status_offset; > }; > > struct mipi_csi2_genpd { > Hi Bryan, could you try to add this change into your PHY driver? This macro format has existed in old arch. We once have such discussion on v5 thread. https://lore.kernel.org/all/bc6abd24-d56a-4fc0-89e9-8986e8d8b3b7@oss.qualcomm.com/ If not applicable, could I put it in KNP series as a fixing in this format? It can save us the effort of merging the re-architected version. We experienced a similar issue with the previous architecture, where additional fixes were needed to accommodate the new platform requirements, leading to considerable time and resource investment. Thanks a lot. Best regards, Hangxiang