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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-851d3640a4bsm1273691b3a.42.2026.08.19.22.25.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Aug 2026 22:25:17 -0700 (PDT) Message-ID: <25c982a2-da65-4710-9412-e3cec66d2c3f@oss.qualcomm.com> Date: Thu, 20 Aug 2026 13:25:13 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: ipq5018: Enable MDIO buses and add ethernet PHY To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260814-qcom_ipq5018_mdio_pinctrl-v2-0-ff90d6605d61@oss.qualcomm.com> <20260814-qcom_ipq5018_mdio_pinctrl-v2-2-ff90d6605d61@oss.qualcomm.com> Content-Language: en-US From: Jie Luo In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=fv3sol4f c=1 sm=1 tr=0 ts=6a868fbf cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=MPq_oieJxT8TesfsIL8A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: 2_tJZyE4wYgMzOaseIb7fn5jfcwKCOL1 X-Proofpoint-ORIG-GUID: 2_tJZyE4wYgMzOaseIb7fn5jfcwKCOL1 X-Proofpoint-Spam-Info: AW1haW4tMjYwODIwMDAzNiBTYWx0ZWRfX9XFeYfQzUyi0 HamX9ce0RRZ/cK+gRbUeYGVvkIS49p2VCTa7A4dQoBWHNUSbgH5bXezkyr8j6hS15tkP63Q4MCp FkKei82glp/draz/HrY/4i8EzwipNC0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIwMDAzNiBTYWx0ZWRfX1Z3J+5SWWAhK 8JEj+CR+6nzzAuf675x0zpMeinJy0nenpWndlPM+DJfAzBUDwS5iNn6Q+UVpm0VHyykzv6jSUF0 AJ4tgFFH1ZGqKxElO8F+UGTELWjKRQhPTNO2I22yKk4yO/PxHvwC0SGD2bhw+U8nr7uJsjEmabh J/FlnJSNWGWFztGWc2U7IGppmi1XF9DL2GWBYddDb7kVKxhKyUH6dzHbTqQCdcjvIKvZelTLL6l OUjJCyraufeMUXqp52xY3oh+ddM0BFKO5cZhEGyp895Ljp5ldavBA1+8BESMGQ6sYWHRMSfPjT2 yk0dch7pFok6GoOii3tdMNpQk8QMslKVr05XobukQWTeRoPOxA/EmBwoe+/Fo479y+r6JEju8z8 1/blbfAiF/crvcftKGK2JnNQhuy8VAKAkRgM5pK/c1LfFou4cBzymTIS+KAY6UdKAq2xQnMgEn4 Mw6NwLWFHj6ayZd7tVA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-19_06,2026-08-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 spamscore=0 adultscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608200036 On 8/19/2026 8:42 PM, Konrad Dybcio wrote: > On 8/14/26 4:22 PM, Luo Jie wrote: >> Both the internal (mdio0) and external (mdio1) MDIO buses are present >> in the SoC dtsi but left disabled at the board level, so the board >> currently has no way to talk to PHYs on either bus. >> >> The RDP432-c2 board uses the SoC-integrated EPHY on mdio0 and an >> external QCA8081 PHY on mdio1 for its Ethernet connections. Enable >> mdio0 and mdio1 with a 6.25MHz MDIO clock, and describe the QCA8081 >> PHY at address 0x1c on mdio1. >> >> Signed-off-by: Luo Jie >> --- >> arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts >> index 33eef92b19b1..aed8359b1931 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts >> @@ -30,6 +30,20 @@ &blsp1_uart1 { >> status = "okay"; >> }; >> >> +&mdio0 { >> + clock-frequency = <6250000>; >> + status = "okay"; > > If the phy is integrated as part of the SoC, is there a reason to > not enable this bus by default for all boards? > All IPQ5018 RDP boards use the integrated PHY and have this bus enabled. I will move it to the SoC-level DTSI so that the bus is enabled by default for all boards. >> +}; >> + >> +&mdio1 { >> + clock-frequency = <6250000>; >> + status = "okay"; > > Nit: a newline before status would be neat I will add the blank line before status in the next revision. Thanks. > >> + >> + ethernet-phy@1c { > > No compatible string and other properties? No compatible string is required here. This PHY QCA8081 supports both Clause 22 and Clause 45 MDIO access, and its PHY ID can be read during probe without any PHY-specific initialization. The standard PHY probing flow is therefore sufficient with only the reg property. > > Konrad