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Mon, 23 Feb 2026 21:21:55 -0800 (PST) X-Received: by 2002:a17:902:e544:b0:2ad:9421:6136 with SMTP id d9443c01a7336-2ad942166b9mr18014465ad.1.1771910515316; Mon, 23 Feb 2026 21:21:55 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad74e34e9csm86344475ad.3.2026.02.23.21.21.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Feb 2026 21:21:55 -0800 (PST) Message-ID: <25e50619-6695-4630-85b4-79c4c88e833c@oss.qualcomm.com> Date: Tue, 24 Feb 2026 10:51:50 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] PCI: dwc: Add helper to Program T_POWER_ON To: Bjorn Helgaas Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20260223153856.GA3695024@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20260223153856.GA3695024@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: EeWeEkW3Jyqeh0MZcuY3guEBDUkD_Fss X-Authority-Analysis: v=2.4 cv=V7twEOni c=1 sm=1 tr=0 ts=699d3574 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=wBt9fhMRhOodALO6grUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI0MDA0MyBTYWx0ZWRfX4v6eeqKgLyra u7n9OQttkZwx2DxfqflczYs5NAgV93hAMpmEDXPsW0hDhgrj1Iw4Zum3nkQMd4z4KhdsVaPJy2h 4uWKMXNP/ef3ldPXshnE5sXvt/Q8BR9nHrAsIuA22wNFjt6Rc4YD+ZToLyxRbOMQkAaoalIb/Mo BNoLeN5jjYbWOBLd6NquOBT2Lb98M/w9cOuaN5+GZpx3vnJDAVs/oqpunYcRSdNXsbbAAfcz2id MwPvLR8Gns+bJBCqXHeQ5T7yV8yjpQbNVeZLKTWe17nvP/OqkGitCN2LszecyvDgGAZdyDPlyYW 9KnX684XC5kyGmWSmuiNOOM9DYopN8Adhy7GAn+z7OzGO+dAezgbvRWOt9z3wgLiqQqzgfgcxKb ghqjMuwo48+ZnoOFv+XRViyf4wb3VAZ6djqX5/HUJpuxYJGfzbxmpojth4ghjvu4odrnviN7suG z07mWXBG5sNbgr0zC7w== X-Proofpoint-GUID: EeWeEkW3Jyqeh0MZcuY3guEBDUkD_Fss X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_06,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602240043 On 2/23/2026 9:08 PM, Bjorn Helgaas wrote: > PCI: dwc: Add dw_pcie_program_t_power_on() helper for L1SS T_POWER_ON > > On Mon, Feb 23, 2026 at 04:43:31PM +0530, Krishna Chaitanya Chundru wrote: >> The T_POWER_ON indicates the time (in μs) that a Port requires the port >> on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# >> asserted before actively driving the interface. This value is used by >> the ASPM driver to compute the LTR_L1.2_THRESHOLD. >> >> Currently, some controllers exposes T_POWER_ON value of zero in the L1SS >> capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations, >> which can result in improper L1.2 exit behavior and can trigger AER's. > s/some controllers exposes/some controllers expose/ > >> Add a helper to override T_POWER_ON value by the DWC controller drivers. > s/a helper/dw_pcie_program_t_power_on()/ > >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/controller/dwc/pcie-designware.c | 27 +++++++++++++++++++++++++++ >> drivers/pci/controller/dwc/pcie-designware.h | 1 + >> 2 files changed, 28 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c >> index 5741c09dde7f40487c6da6dfd66f7c8d96a74259..f56e2c07ddc57bd84882c14bebc7d4b4961f601a 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.c >> +++ b/drivers/pci/controller/dwc/pcie-designware.c >> @@ -1249,6 +1249,33 @@ void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci) >> dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); >> } >> >> +/* TODO: Need to handle multi root ports */ >> +void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on) >> +{ >> + u8 scale, value; >> + u16 offset; >> + u32 val; >> + >> + if (!t_power_on) >> + return; >> + >> + offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); >> + if (offset) { > if (!offset) > return; > >> + pcie_encode_t_power_on(t_power_on, &scale, &value); >> + >> + dw_pcie_dbi_ro_wr_en(pci); >> + >> + val = readl(pci->dbi_base + offset + PCI_L1SS_CAP); >> + val &= ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE); >> + val |= FIELD_PREP(PCI_L1SS_CAP_P_PWR_ON_SCALE, scale); >> + val |= FIELD_PREP(PCI_L1SS_CAP_P_PWR_ON_VALUE, value); > FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_SCALE, ®, scale); > FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_VALUE, ®, value); ack, I will fix all the comments in next series. - Krishna Chaitanya. >> + writel(val, pci->dbi_base + offset + PCI_L1SS_CAP); >> + >> + dw_pcie_dbi_ro_wr_dis(pci); >> + } >> +} >> + >> void dw_pcie_setup(struct dw_pcie *pci) >> { >> u32 val; >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h >> index ae6389dd9caa5c27690f998d58729130ea863984..da67beece3f11e33d9a1937fa23d443feea3bbc7 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.h >> +++ b/drivers/pci/controller/dwc/pcie-designware.h >> @@ -602,6 +602,7 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, >> u8 bar, size_t size); >> void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); >> void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci); >> +void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on); >> void dw_pcie_setup(struct dw_pcie *pci); >> void dw_pcie_iatu_detect(struct dw_pcie *pci); >> int dw_pcie_edma_detect(struct dw_pcie *pci); >> >> -- >> 2.34.1 >>