From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15D323E022A for ; Thu, 11 Jun 2026 23:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781222307; cv=none; b=HZAdnzPIB2XjHJIVJUPOUJfVjRI+j3xXd47+2MxRn3cUjVuujKJFDawf0QOhaHUf65FTNrSewGJnvQye1fqrv8gVJdjAcE0VJ3U7V73trkquTbYvEjcfMLVIbc80GpE1mB0toE1d9oi7L2ZSMWERuscKAUTRjQwMZYxxnEyjRCU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781222307; c=relaxed/simple; bh=ypszbHyzB39x79bcGaB6iFn+Y2ljrD/Div0NqvLkCCw=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=jWhhb5tP1KFdoKP5xEGisJHUyZcOZA6JpGFNZDtckcOs86L/XDTWRXCeFhaa6eKQbq1pz28HWFhnD1Lxbl0e5YS1Ruy+n2PvsJ7LQjY5H2ZDivKME6RtpN+qxqEn+C17qSrEJOIJj7QT/plVycptmiHZZ72woKJXqDyDnwq5NAs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=UQIZwuIN; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="UQIZwuIN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1781222299; bh=ypszbHyzB39x79bcGaB6iFn+Y2ljrD/Div0NqvLkCCw=; h=Date:Subject:From:To:Cc:References:In-Reply-To:From; b=UQIZwuINbbo1Gsuv/8GDU95NlR1SVDlU/WBPSgbAkgafvPSpVxq/rUa5sGRctCvHR AvQUY9nUEE40TN3oREpbavfacRDXhf1WEOrFZfxkudAAd95M+7tKF2M2RsncYYlFX3 WXi6J19/BO4tphd+y0pjwCN+S3EJ4jCl8EyT7Y2QeWi6faQhez/5SJGetgFhcC3DEm zws31jK420nNdX1HsO0DUpOqFyycHFlacnGtwTO0QNzXMDwccr640I2+qYVBc5bH43 bHhdg1irQvFXGL7m43avpv+dVxjOlk7kLcOfNjaN2tQ93WzIVYWdQG7d+J6OR4eBp/ 57e5DlKRHRUFg== Received: from [100.64.0.241] (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8BD2517E0416; Fri, 12 Jun 2026 01:58:18 +0200 (CEST) Message-ID: <25f0a87d-0607-49eb-b297-b45c11b4df1b@collabora.com> Date: Fri, 12 Jun 2026 02:58:18 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups From: Cristian Ciocaltea To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?Q?Thomas_Niederpr=C3=BCm?= , Simon Wright References: <20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com> Content-Language: en-US In-Reply-To: <20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, On 6/11/26 3:31 PM, Cristian Ciocaltea wrote: > This series provides a set of bug fixes and cleanups for the Rockchip > Samsung HDPTX PHY driver. > > The first part of the series (i.e. PATCH 1 & 2) addresses clock rate > calculation and synchronization issues. Specifically, it fixes edge > cases where the PHY PLL is pre-programmed by an external component (like > a bootloader) or when changing the color depth (bpc) while keeping the > modeline constant. Because the Common Clock Framework .set_rate() > callback might not be invoked if the pixel clock remains unchanged, this > previously led to out-of-sync states between CCF and the actual HDMI PHY > configuration. > > The second part focuses on code cleanups and modernizing the register > access. Now that dw_hdmi_qp driver has fully switched to using > phy_configure(), we can drop the deprecated TMDS rate setup workarounds > and the restrict_rate_change flag logic. Finally, it refactors the > driver to consistently use standard bitfield macros. > > Signed-off-by: Cristian Ciocaltea > --- > Changes in v3: > - Replaced div_u64() with DIV_ROUND_CLOSEST_ULL() in Patch 1 (Sashiko) > - Fixed theoretical usage_count unbalanced issue in Patch 2 (Sashiko) > - Rebased series onto latest phy/next > - Link to v2: https://patch.msgid.link/20260511-hdptx-clk-fixes-v2-0-664e41379cab@collabora.com Please use v4 as I added two more patches to address latest findings from Sashiko: https://lore.kernel.org/all/20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com/ Thanks, Cristian