From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: "David E. Box" <david.e.box@linux.intel.com>
Cc: linux-kernel@vger.kernel.org,
platform-driver-x86@vger.kernel.org,
ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com
Subject: Re: [PATCH 02/11] platform/x86/intel/vsec: Add base address field
Date: Tue, 26 Sep 2023 17:39:52 +0300 (EEST) [thread overview]
Message-ID: <25fec2f6-b01f-1488-fcdc-8986ab452a78@linux.intel.com> (raw)
In-Reply-To: <20230922213032.1770590-3-david.e.box@linux.intel.com>
[-- Attachment #1: Type: text/plain, Size: 4498 bytes --]
On Fri, 22 Sep 2023, David E. Box wrote:
> Some devices may emulate PCI VSEC capabilities in MMIO. In such cases the
> BAR is not readable from a config space. Provide a field for drivers to
> indicate the base address to be used.
>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> ---
> drivers/platform/x86/intel/pmt/class.c | 14 +++++++++++---
> drivers/platform/x86/intel/vsec.c | 10 ++++++++--
> drivers/platform/x86/intel/vsec.h | 2 ++
> 3 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c
> index 2ad91d2fd954..32608baaa56c 100644
> --- a/drivers/platform/x86/intel/pmt/class.c
> +++ b/drivers/platform/x86/intel/pmt/class.c
> @@ -160,10 +160,11 @@ static struct class intel_pmt_class = {
>
> static int intel_pmt_populate_entry(struct intel_pmt_entry *entry,
> struct intel_pmt_header *header,
> - struct device *dev,
> + struct intel_vsec_device *ivdev,
> struct resource *disc_res)
> {
> - struct pci_dev *pci_dev = to_pci_dev(dev->parent);
> + struct pci_dev *pci_dev = ivdev->pcidev;
> + struct device *dev = &ivdev->auxdev.dev;
> u8 bir;
>
> /*
> @@ -215,6 +216,13 @@ static int intel_pmt_populate_entry(struct intel_pmt_entry *entry,
>
> break;
> case ACCESS_BARID:
> + /* Use the provided base address if it exists */
> + if (ivdev->base_addr) {
> + entry->base_addr = ivdev->base_addr +
> + GET_ADDRESS(header->base_offset);
> + break;
> + }
> +
> /*
> * If another BAR was specified then the base offset
> * represents the offset within that BAR. SO retrieve the
> @@ -319,7 +327,7 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry, struct intel_pmt_namespa
> if (ret)
> return ret;
>
> - ret = intel_pmt_populate_entry(entry, &header, dev, disc_res);
> + ret = intel_pmt_populate_entry(entry, &header, intel_vsec_dev, disc_res);
> if (ret)
> return ret;
>
> diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c
> index c5d0202068cf..e0dd64dec9eb 100644
> --- a/drivers/platform/x86/intel/vsec.c
> +++ b/drivers/platform/x86/intel/vsec.c
> @@ -150,6 +150,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he
> struct intel_vsec_device *intel_vsec_dev;
> struct resource *res, *tmp;
> unsigned long quirks = info->quirks;
> + u64 base_addr;
> int i;
>
> if (!intel_vsec_supported(header->id, info->caps))
> @@ -178,14 +179,18 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he
> if (quirks & VSEC_QUIRK_TABLE_SHIFT)
> header->offset >>= TABLE_OFFSET_SHIFT;
>
> + if (info->base_addr)
> + base_addr = info->base_addr;
> + else
> + base_addr = pdev->resource[header->tbir].start;
> +
> /*
> * The DVSEC/VSEC contains the starting offset and count for a block of
> * discovery tables. Create a resource array of these tables to the
> * auxiliary device driver.
> */
> for (i = 0, tmp = res; i < header->num_entries; i++, tmp++) {
> - tmp->start = pdev->resource[header->tbir].start +
> - header->offset + i * (header->entry_size * sizeof(u32));
> + tmp->start = base_addr + header->offset + i * (header->entry_size * sizeof(u32));
> tmp->end = tmp->start + (header->entry_size * sizeof(u32)) - 1;
> tmp->flags = IORESOURCE_MEM;
>
> @@ -203,6 +208,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he
> intel_vsec_dev->resource = res;
> intel_vsec_dev->num_resources = header->num_entries;
> intel_vsec_dev->quirks = info->quirks;
> + intel_vsec_dev->base_addr = info->base_addr;
>
> if (header->id == VSEC_ID_SDSI)
> intel_vsec_dev->ida = &intel_vsec_sdsi_ida;
> diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel/vsec.h
> index ab0f161f86c5..bddd33e1c17e 100644
> --- a/drivers/platform/x86/intel/vsec.h
> +++ b/drivers/platform/x86/intel/vsec.h
> @@ -73,6 +73,7 @@ struct intel_vsec_platform_info {
> struct intel_vsec_header **headers;
> unsigned long caps;
> unsigned long quirks;
> + u64 base_addr;
> };
>
> struct intel_vsec_device {
> @@ -84,6 +85,7 @@ struct intel_vsec_device {
> void *priv_data;
> size_t priv_data_size;
> unsigned long quirks;
> + u64 base_addr;
> };
>
> int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent,
>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
--
i.
next prev parent reply other threads:[~2023-09-26 14:40 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-22 21:30 [PATCH 00/11] intel_pmc: Add telemetry API to read counters David E. Box
2023-09-22 21:30 ` [PATCH 01/11] platform/x86/intel/vsec: Add intel_vsec_register David E. Box
2023-09-26 14:17 ` Ilpo Järvinen
2023-09-26 23:51 ` David E. Box
2023-09-22 21:30 ` [PATCH 02/11] platform/x86/intel/vsec: Add base address field David E. Box
2023-09-26 14:39 ` Ilpo Järvinen [this message]
2023-09-22 21:30 ` [PATCH 03/11] platform/x86/intel/pmt: Add header to struct intel_pmt_entry David E. Box
2023-09-26 14:43 ` Ilpo Järvinen
2023-09-22 21:30 ` [PATCH 04/11] platform/x86/intel/pmt: telemetry: Export API to read telemetry David E. Box
2023-09-26 15:40 ` Ilpo Järvinen
2023-09-26 23:59 ` David E. Box
2023-09-22 21:30 ` [PATCH 05/11] platform/x86:intel/pmc: Move get_low_power_modes function David E. Box
2023-09-26 15:56 ` Ilpo Järvinen
2023-09-27 0:16 ` David E. Box
2023-09-22 21:30 ` [PATCH 06/11] platform/x86/intel/pmc: Split pmc_core_ssram_get_pmc() David E. Box
2023-09-22 21:30 ` [PATCH 07/11] platform/x86/intel/pmc: Find and register PMC telemetry entries David E. Box
2023-09-22 21:30 ` [PATCH 08/11] platform/x86/intel/pmc: Display LPM requirements for multiple PMCs David E. Box
2023-09-22 21:30 ` [PATCH 09/11] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT David E. Box
2023-09-26 16:07 ` Ilpo Järvinen
2023-09-22 21:30 ` [PATCH 10/11] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P David E. Box
2023-09-26 16:03 ` Ilpo Järvinen
2023-09-27 0:20 ` David E. Box
2023-09-22 21:30 ` [PATCH 11/11] platform/x86/intel/pmc: Add debug attribute for Die C6 counter David E. Box
2023-09-26 16:11 ` Ilpo Järvinen
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