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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CY6PEPF0000004D.mail.protection.outlook.com (10.167.247.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.522.6 via Frontend Transport; Tue, 13 Oct 2026 17:51:46 +0000 Received: from purico-9dcchost.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Tue, 13 Oct 2026 12:51:40 -0500 From: Melody Wang To: CC: LKML , Tom Lendacky , , Melody Wang Subject: [PATCH v4 3/7] x86/sev: Route unsupported APIC register accesses to the hypervisor APIC emulation Date: Tue, 13 Oct 2026 17:50:50 +0000 Message-ID: <2646bd1474e25dcb837fef5a3c24269664432a8a.1791912902.git.huibo.wang@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY6PEPF0000004D:EE_|DS0PR12MB7876:EE_ X-MS-Office365-Filtering-Correlation-Id: 86408cac-0605-4439-45f3-08df2952a685 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|23010399003|82310400026|11063799006|56012099006|261009223027099003|22082099003|18002099003|3023799007|10067099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PjJ/YUVJYOl/nGyLmOqROGyzKbYlUDEo8A7tQzvTeiKbaNiU5v9U/f/Yn6DVkijS2GvMt5Sdl3864UQn3mn4vBJ/JRMw62J6FPbMaG8zgnCkRS9cA74ue2dJ6u3N40iJr/L6FV18cEP1kSYMHMpcvAnV0+BMi+cIsqMRoXOXuQZUkacXffgniQ8z8jYg6PkdNsrfYiY70FMbsFNw/Trw5rGOLqrSbOsFS4qbISLS1L6XewxlekcPO/fbSN/iIj2SwQNvzk4jm7M1pSNtAUd5zbANip99wGpMhjnnK+pq2upZ4FF3by+vuL4pRfZYzroJQq9lJRDTXSNQ/GGjpv2Zl+JzcJZPA7Q0Qa7V0dUZopT91S+LUMug0n1q/VVdbSEkI53V714DzrCstt/cWATVjtINUu22ozylaEvERTQvLsmQQhMCdoIWGlsLgltvCRef X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2026 17:51:46.6808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86408cac-0605-4439-45f3-08df2952a685 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY6PEPF0000004D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7876 The SVSM APIC emulation supports only a subset of the X2APIC MSRs. Right now only basic APIC functionality related to interrupt delivery is supported. Therefore, route the unsupported ones to the hypervisor's X2APIC emulation. Signed-off-by: Melody Wang --- arch/x86/coco/sev/core.c | 46 +++++++++++------------------ arch/x86/include/asm/sev-common.h | 1 + arch/x86/include/asm/sev.h | 8 ++--- arch/x86/kernel/apic/x2apic_savic.c | 8 ++--- arch/x86/kernel/apic/x2apic_svsm.c | 11 +++++-- 5 files changed, 35 insertions(+), 39 deletions(-) diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index 900a7ff8b639..99df8d7f3e98 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -972,7 +972,7 @@ int __init sev_es_efi_map_ghcbs_cas(pgd_t *pgd) return 0; } -u64 savic_ghcb_msr_read(u32 reg) +static u64 __sev_apic_ghcb_msr_rw(u32 reg, u64 value, bool write) { u64 msr = APIC_BASE_MSR + (reg >> 4); struct pt_regs regs = { .cx = msr }; @@ -981,49 +981,37 @@ u64 savic_ghcb_msr_read(u32 reg) enum es_result res; struct ghcb *ghcb; + if (write) { + regs.ax = lower_32_bits(value); + regs.dx = upper_32_bits(value); + } + guard(irqsave)(); ghcb = __sev_get_ghcb(&state); vc_ghcb_invalidate(ghcb); - res = __vc_handle_msr(ghcb, &ctxt, false); + res = __vc_handle_msr(ghcb, &ctxt, write); if (res != ES_OK) { - pr_err("Secure AVIC MSR (0x%llx) read returned error (%d)\n", msr, res); - /* MSR read failures are treated as fatal errors */ - sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_SAVIC_FAIL); + pr_err("APIC MSR via GHCB (0x%llx) %s returned error (%d)\n", msr, write ? "write" : "read", res); + /* MSR read/write failures are treated as fatal errors */ + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_APIC_MSR_FAIL); } __sev_put_ghcb(&state); + /* The return value will be ignored by the caller for a write */ return regs.ax | regs.dx << 32; } -void savic_ghcb_msr_write(u32 reg, u64 value) +u64 sev_apic_ghcb_msr_read(u32 reg) { - u64 msr = APIC_BASE_MSR + (reg >> 4); - struct pt_regs regs = { - .cx = msr, - .ax = lower_32_bits(value), - .dx = upper_32_bits(value) - }; - struct es_em_ctxt ctxt = { .regs = ®s }; - struct ghcb_state state; - enum es_result res; - struct ghcb *ghcb; - - guard(irqsave)(); - - ghcb = __sev_get_ghcb(&state); - vc_ghcb_invalidate(ghcb); - - res = __vc_handle_msr(ghcb, &ctxt, true); - if (res != ES_OK) { - pr_err("Secure AVIC MSR (0x%llx) write returned error (%d)\n", msr, res); - /* MSR writes should never fail. Any failure is fatal error for SNP guest */ - sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_SAVIC_FAIL); - } + return __sev_apic_ghcb_msr_rw(reg, 0, false); +} - __sev_put_ghcb(&state); +void sev_apic_ghcb_msr_write(u32 reg, u64 value) +{ + __sev_apic_ghcb_msr_rw(reg, value, true); } enum es_result savic_register_gpa(u64 gpa) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 095fbafe8a2c..585ddc44b6b4 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -210,6 +210,7 @@ struct snp_psc_desc { #define GHCB_TERM_SVSM_CA_REMAP_FAIL 11 /* SVSM is present but CA could not be remapped */ #define GHCB_TERM_SAVIC_FAIL 12 /* Secure AVIC-specific failure */ #define GHCB_TERM_ALT_INJ_FAIL 13 /* Alternate Injection-specific failure */ +#define GHCB_TERM_APIC_MSR_FAIL 14 /* APIC MSR failure */ #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index ea248d9e1c49..93161b663d9b 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -541,8 +541,8 @@ void __init snp_secure_tsc_prepare(void); void __init snp_secure_tsc_init(void); enum es_result savic_register_gpa(u64 gpa); enum es_result savic_unregister_gpa(u64 *gpa); -u64 savic_ghcb_msr_read(u32 reg); -void savic_ghcb_msr_write(u32 reg, u64 value); +u64 sev_apic_ghcb_msr_read(u32 reg); +void sev_apic_ghcb_msr_write(u32 reg, u64 value); static __always_inline void vc_ghcb_invalidate(struct ghcb *ghcb) { @@ -650,8 +650,8 @@ static inline void __init snp_secure_tsc_init(void) { } static inline void sev_evict_cache(void *va, int npages) {} static inline enum es_result savic_register_gpa(u64 gpa) { return ES_UNSUPPORTED; } static inline enum es_result savic_unregister_gpa(u64 *gpa) { return ES_UNSUPPORTED; } -static inline void savic_ghcb_msr_write(u32 reg, u64 value) { } -static inline u64 savic_ghcb_msr_read(u32 reg) { return 0; } +static inline void sev_apic_ghcb_msr_write(u32 reg, u64 value) { } +static inline u64 sev_apic_ghcb_msr_read(u32 reg) { return 0; } #endif /* CONFIG_AMD_MEM_ENCRYPT */ diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c index 4bc6d7e018a5..990e4a379e07 100644 --- a/arch/x86/kernel/apic/x2apic_savic.c +++ b/arch/x86/kernel/apic/x2apic_savic.c @@ -72,7 +72,7 @@ static u32 savic_read(u32 reg) case APIC_LVT0: case APIC_LVT1: case APIC_LVTERR: - return savic_ghcb_msr_read(reg); + return sev_apic_ghcb_msr_read(reg); case APIC_ID: case APIC_LVR: case APIC_TASKPRI: @@ -193,7 +193,7 @@ static void savic_icr_write(u32 icr_low, u32 icr_high) icr_data = ((u64)icr_high) << 32 | icr_low; if (dsh != APIC_DEST_SELF) - savic_ghcb_msr_write(APIC_ICR, icr_data); + sev_apic_ghcb_msr_write(APIC_ICR, icr_data); apic_set_reg64(this_cpu_ptr(savic_page), APIC_ICR, icr_data); } @@ -210,7 +210,7 @@ static void savic_write(u32 reg, u32 data) case APIC_LVTTHMR: case APIC_LVTPC: case APIC_LVTERR: - savic_ghcb_msr_write(reg, data); + sev_apic_ghcb_msr_write(reg, data); break; case APIC_TASKPRI: case APIC_EOI: @@ -316,7 +316,7 @@ static void savic_eoi(void) * interrupts. Return to the guest from GHCB protocol event takes * care of re-evaluating interrupt state. */ - savic_ghcb_msr_write(APIC_EOI, 0); + sev_apic_ghcb_msr_write(APIC_EOI, 0); } else { /* * Hardware clears APIC_ISR and re-evaluates the interrupt state diff --git a/arch/x86/kernel/apic/x2apic_svsm.c b/arch/x86/kernel/apic/x2apic_svsm.c index 6edfbcca2958..0a89c5b357f0 100644 --- a/arch/x86/kernel/apic/x2apic_svsm.c +++ b/arch/x86/kernel/apic/x2apic_svsm.c @@ -81,8 +81,15 @@ static u32 __svsm_apic_msr_rw(u32 reg, u32 v, bool write) } break; default: - pr_err("%s 0x%x not supported\n", call_reg_str, reg); - return 0; + if (write) { + /* + * Even if this will end up returning call.rdx_out, + * that is being ignored by the caller for a write. + */ + sev_apic_ghcb_msr_write(reg, v); + } else { + return sev_apic_ghcb_msr_read(reg); + } } return call.rdx_out; -- 2.43.0