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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.googlemail.com with ESMTPSA id 8sm3095771wrz.57.2022.01.20.03.28.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Jan 2022 03:28:11 -0800 (PST) Message-ID: <2688b779-9cb8-b6ea-f8cc-93bc8ddf72f3@redhat.com> Date: Thu, 20 Jan 2022 12:28:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.4.0 Subject: Re: [PATCH v2 0/7] kvm: fix latent guest entry/exit bugs Content-Language: en-US To: Mark Rutland , Christian Borntraeger Cc: linux-kernel@vger.kernel.org, Michael Ellerman , aleksandar.qemu.devel@gmail.com, alexandru.elisei@arm.com, anup.patel@wdc.com, aou@eecs.berkeley.edu, atish.patra@wdc.com, bp@alien8.de, catalin.marinas@arm.com, chenhuacai@kernel.org, dave.hansen@linux.intel.com, frankja@linux.ibm.com, frederic@kernel.org, gor@linux.ibm.com, hca@linux.ibm.com, james.morse@arm.com, jmattson@google.com, joro@8bytes.org, luto@kernel.org, maz@kernel.org, mingo@redhat.com, nsaenzju@redhat.com, palmer@dabbelt.com, paulmck@kernel.org, paul.walmsley@sifive.com, peterz@infradead.org, seanjc@google.com, suzuki.poulose@arm.com, svens@linux.ibm.com, tglx@linutronix.de, tsbogend@alpha.franken.de, vkuznets@redhat.com, wanpengli@tencent.com, will@kernel.org, Anup Patel , Atish Patra References: <20220119105854.3160683-1-mark.rutland@arm.com> <20220119192217.GD43919@C02TD0UTHF1T.local> From: Paolo Bonzini In-Reply-To: <20220119192217.GD43919@C02TD0UTHF1T.local> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/19/22 20:22, Mark Rutland wrote: > I wonder, is the s390 guest entry/exit*preemptible* ? > > If a timer IRQ can preempt in the middle of the EQS, we wouldn't balance > things before a ctx-switch to the idle thread, which would then be able > to hit this. > > I'll need to go audit the other architectures for similar. They don't enable interrupts in the entry/exit path so they should be okay. RISC-V and x86 have an explicit preempt_disable/enable, while MIPS only has local_irq_disable/enable. (MIPS is a mess of dead code, I have patches to clean it up). Paolo